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參數(shù)資料
| 型號(hào)： | LMX1600 |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | PLLatinum Low Cost Dual Frequency Synthesizer(PLLatinum技術(shù)低耗雙通道頻率合成器) |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 2000 MHz, PDSO16 |
| 封裝： | PLASTIC, TSSOP-16 |
| 文件頁(yè)數(shù)： | 7/16頁(yè) |
| 文件大小： | 217K |
| 代理商： | LMX1600 |
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1.0 Functional Description
(Continued)
the phase detector inputs is less than 15 ns for 4 consecutive
comparison cycles. The lock detect output is low when the
error between the phase detector outputs is more than 30 ns
for one comparison cycle. The lock detect output is always
low when the PLL is in power down mode. For further de-
scription see Programming Description 2.5.
1.9
Each PLL is individually power controlled by the device
EN
pin. The
EN
MAIN
controls the Main PLL, and the
EN
AUX
con-
trols the Aux PLL. Activation of
EN
= LOW (power down)
condition results in the disabling of the respective N and R
counters and de-biasing of their respective fin inputs (to a
high impedance state). The reference oscillator input block
powers down and the OSC
pin reverts to a high impedance
state only when both
EN
pins are LOW. Power down forces
the respective charge pump and phase comparator logic to a
TRI-STATE condition as well as disabling the bandgap refer-
ence block. Power up occurs immediately when the
EN
pin is
brought high. Power up sequence: Bandgap and Oscillator
blocks come up first, with the remaining PLL functions be-
coming active approx. 1 μs later. All programming informa-
tion is retained internally in the chip when in power down
mode. The MICROWIRE control register remains active and
capable of loading and latching in data during power down
mode.
POWER CONTROL
2.0
Programming Description
2.1
The descriptions below detail the 18-bit data register loaded through the MICROWIRE Interface. The 18-bit shift register is used
to program the 12-bit Main and Aux R counter registers and the 16-bit Main and Aux N counter registers. The shift register con-
sists of a 16-bit DATA field and a 2-bit control (CTL [1:0]) field as shown below. The control bits decode the internal register ad-
dress. On the rising edge of LE, data stored in the shift register is loaded into one of the 4 appropriate latches (selected by ad-
dress bits). Data is shifted in MSB first.
MICROWIRE INTERFACE
MSB
LSB
DATA [15:0]
CTL [1:0]
18
2
1
0
2.1.1
When LE transitions high, data is transferred from the 18-bit shift register into one of the 4 appropriate internal latches depending
upon the state of the control (CTL) bits. The control bits decode the internal register address
Register Location Truth Table
CTL [1:0]
DATA Location
AUX_R Register
AUX_N Register
MAIN_R Register
MAIN_N Register
0
0
1
1
0
1
0
1
2.1.2
Register Content Truth Table
First Bit
17
SHIFT REGISTER BIT LOCATION
11
10
9
AUX_R_CNTR
AUX_B_CNTR
Last Bit
1
0
0
1
1
16
15
14
13
12
8
7
6
5
4
3
2
0
0
1
0
1
AUX_R
AUX_N
MAIN_R
MAIN_N
FoLD
AUX_A_CNTR
CP_WORD
MAIN_R_CNTR
MAIN_B_CNTR and MAIN_A_CNTR
2.2
PROGRAMMABLE REFERENCE DIVIDERS
2.2.1
If the Control Bits (CTL [1:0]) are 0 0 when LE transitions high, data is transferred from the 18-bit shift register into a latch which
sets the Aux PLL 12-bit R counter divide ratio. The divide ratio is programmed using the bits
AUX_R_CNTR
as shown in table
2.2.3. The divider ratio must be
≥
2. The FoLD word bits controls the multifunction FoLD output as described in section in 2.5.
AUX_R Register
First Bit
17
SHIFT REGISTER BIT LOCATION
11
10
9
AUX_R_CNTR[11:0]
Last Bit
1
0
16
FoLD[3:0]
15
14
13
12
8
7
6
5
4
3
2
0
0
AUX_R
L
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LMX1600_05 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PLLatinum⑩ Low Cost Dual Frequency Synthesizer |
| LMX1600EVAL | 功能描述:其他開發(fā)工具 LOW COST DUAL PLL EVAL BOARD RoHS:否 制造商:Parallax 產(chǎn)品:ELEV-8 Hex Upgrade Kits 類型:Robotics 工具用于評(píng)估:ELEV-8 Quadcopter 工作電源電壓: |
| LMX1600SLB | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PLLatinum⑩ Low Cost Dual Frequency Synthesizer |
| LMX1600SLBX | 制造商:Rochester Electronics LLC 功能描述: 制造商:Texas Instruments 功能描述: |
| LMX1600SLBX/NOPB | 功能描述:IC FREQ SYNTH DUAL 16LAMINATECSP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
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