參數(shù)資料
型號: LMV841
廠商: National Semiconductor Corporation
英文描述: CMOS Input, RRIO, Wide Supply Range Operational Amplifier
中文描述: CMOS輸入,RRIO,寬電源電壓范圍運算放大器
文件頁數(shù): 4/16頁
文件大?。?/td> 899K
代理商: LMV841
±5V Electrical Characteristics
(Note 4)
Unless otherwise specified, all limits are guaranteed for at T
A
= 25°C, V
+
= 5V, V
= –5V, V
CM
= 0V, and R
L
> 10 M
to V
CM
.
Boldface
limits apply at the temperature extremes.
Symbol
Parameter
Conditions
Min
(Note 6)
Typ
(Note 5)
–17
Max
(Note 6)
±500
±800
±5
Units
V
OS
Input Offset Voltage
μ
V
TCV
OS
I
B
Input Offset Voltage Drift (Note 7)
0.25
μ
V/°C
Input Bias Current
(Notes 7, 8)
Input Offset Current
0.3
10
300
pA
I
OS
CMRR
–5V
V
CM
5V
40
fA
Common Mode Rejection Ratio
86
80
86
82
–5.2
100
dB
PSRR
Power Supply Rejection Ratio
2.7V
V
+
12V, V
O
= 0V
100
dB
CMVR
Input Common-Mode Voltage Range
CMRR
50 dB
R
L
= 2 k
V
O
= –4.7V to 4.7V
R
L
= 10 k
V
O
= –4.8V to 4.8V
R
L
= 2 k
to 0V
5.2
V
A
VOL
Large Signal Voltage Gain
100
96
118
dB
100
96
129
V
O
Output Swing High,
measured from V
+
88
120
155
75
95
125
140
50
70
mV
R
L
= 10 k
to 0V
40
Output Swing Low,
measured from V
-
R
L
= 2 k
to 0V
85
mV
R
L
= 10 k
to 0V
36
I
O
Output Short Circuit Current
(Notes 3, 9)
Sourcing V
O
= 0V
V
IN
= 100 mV
Sourcing V
O
= 0V
V
IN
= 100 mV
25
20
30
mA
25
20
30
I
S
Supply Current
1.11
1.7
2
mA
SR
Slew Rate (Note 10)
A
V
= +1, V
O
= 9 V
PP
10% to 90%
2.5
V/
μ
s
GBW
Φ
m
e
n
R
OUT
Gain Bandwidth Product
Phase Margin
4.5
67
MHz
Deg
Input-Referred Voltage Noise
f = 1 kHz
20
nV/
Open Loop Output Impedance
f = 3 MHz
70
Ω
Note 1:
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see the Electrical Characteristics
Tables.
Note 2:
Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC) Field-
Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
Note 3:
The maximum power dissipation is a function of T
, θ
, and T
. The maximum allowable power dissipation at any ambient temperature is
P
D
= (T
J(MAX)
- T
A
)/ θ
JA
. All numbers apply for packages soldered directly onto a PC board.
Note 4:
Electrical table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating
of the device.
Note 5:
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will
also depend on the application and configuration. The typical values are not tested and are not guaranteed on shipped production material.
Note 6:
Limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlations using statistical quality
control (SQC) method.
Note 7:
This parameter is guaranteed by design and/or characterization and is not tested in production.
Note 8:
Positive current corresponds to current flowing into the device.
www.national.com
4
L
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