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參數(shù)資料
| 型號(hào)： | LMV111M7X |
| 廠(chǎng)商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類(lèi)： | 運(yùn)算放大器 |
| 英文描述： | Operational Amplifier with Bias Network |
| 中文描述： | OP-AMP, 1 MHz BAND WIDTH, PDSO5 |
| 封裝： | SC-70, 5 PIN |
| 文件頁(yè)數(shù)： | 6/9頁(yè) |
| 文件大小： | 337K |
| 代理商： | LMV111M7X |
Typical Performance Characteristics
(Unless otherwise specified, V
S
= +5V, single supply, T
A
=
25C.) (Continued)
Application Section
The LMV111 integrates a rail-to-rail op amp and a V
+
/2 bias
circuit into one ultra tiny package. With its small footprint and
reduced component count for bias network, it enables the
design of smaller portable electronic products, such as cellu-
lar phones, pagers, PDAs, PCMCIA cards, etc. In addition,
the integration solution minimizes printed circuit board stray
capacitance, and reduces the complexity of circuit design.
The core op amp of this family is National’s LMV321.
1.0 Supply Bypassing
The application circuits in this datasheet do not show the
power supply connections and the associated bypass ca-
pacitors for simplification. When the circuits are built, it is al-
ways required to have bypass capacitors. Ceramic disc ca-
pacitors (0.1μF) or solid tantalum (1μF) with short leads, and
located close to the IC are usually necessary to prevent in-
terstage coupling through the power supply internal imped-
ance. Inadequate bypassing will manifest itself by a low fre-
quency
oscillation
or
by
high
Sometimes, a 10μF (or larger) capacitor is used to absorb
low frequency variations and a smaller 0.1μF disc is paral-
leled across it to prevent any high frequency feedback
through the power supply lines.
2.0 Input Voltage Range
The input voltage should be within the supply rails. The ESD
protection circuitry at the input of the device includes a diode
between the input pin and the negative supply pin. Driving
the input more than 0.6V (at 25C) beyond the negative sup-
ply will turn on the diode and cause signal distortions.
3.0 Capacitive Load Tolerance
The LMV111 can directly drive 200pF capacitive load with
unity gain without oscillation. The unity-gain follower is the
most sensitive configuration to capacitive loading. Direct ca-
pacitive loading reduces the phase margin of amplifiers. The
combination of the amplifier’s output impedance and the ca-
pacitive load induces phase lag. This results in either an un-
derdamped pulse or oscillation. To drive a heavier capacitive
load, a resistive isolation can be used as shown in Figure 1
frequency
instabilities.
The isolation resistor R
and the C
form a pole to increase
stability by adding more phase margin to the overall system.
The desired performance depends on the value of R
. A
50
to 100
isolation resistor is recommended for initial
evaluation. The bigger the R
iso
resistor value, the more
stable V
OUT
will be.
Output Voltage Swing vs.
Supply Voltage
DS101262-22
DS101262-23
FIGURE 1. Resistive Isolation of a Heavy Capacitive
Load
L
www.national.com
6
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LMV112 | 制造商:NSC 制造商全稱(chēng):National Semiconductor 功能描述:40 MHz Dual Clock Buffer |
| LMV112 WAF | 制造商:Texas Instruments 功能描述: |
| LMV112SD | 功能描述:時(shí)鐘緩沖器 RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| LMV112SD/NOPB | 功能描述:時(shí)鐘緩沖器 40Mhz Dual Clock Bfr RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| LMV112SD/NOPB | 制造商:Texas Instruments 功能描述:Buffer IC |
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