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參數(shù)資料
| 型號(hào)： | LMU112JC50 |
| 廠商： | LOGIC DEVICES INC |
| 元件分類： | 數(shù)字信號(hào)處理外設(shè) |
| 英文描述： | Silver Mica Capacitor; Capacitance:22pF; Capacitance Tolerance:+/- 5%; Series:CD15; Voltage Rating:300VDC; Capacitor Dielectric Material:Mica; Termination:Radial Leaded; Lead Pitch:5.9mm; Leaded Process Compatible:No RoHS Compliant: No |
| 中文描述： | 12-BIT, DSP-MULTIPLIER, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁數(shù)： | 1/6頁 |
| 文件大小： | 46K |
| 代理商： | LMU112JC50 |
DEVICES INCORPORATED
LMU112
12 x 12-bit Parallel Multiplier
12 x 12-bit Parallel Multiplier
Multipliers
08/16/2000–LDS.112-K
1
K
25 ns Worst-Case Multiply Time
K
Low Power CMOS Technology
K
Replaces Fairchild MPY112K
K
Two’s Complement or Unsigned
Operands
K
Three-State Outputs
K
Package Styles Available:
48-pin PDIP
52-pin PLCC, J-Lead
FEATURES
DESCRIPTION
DEVICES INCORPORATED
The
LMU112
is a high-speed, low
power 12-bit parallel multiplier built
using advanced CMOS technology.
The LMU112 is pin and functionally
compatible with Fairchilds’s MPY112K.
The A and B input operands are
loaded into their respective registers
on the rising edge of the separate
clock inputs (CLK A and CLK B).
Two’s complement or unsigned
magnitude operands are accommo-
dated via the operand control bit (TC)
LMU112 B
LOCK
D
IAGRAM
A REGISTER
CLK A
CLK B
12
12
24
OE
B
11-0
A
11-0
R
23-8
TC
FORMAT ADJUST
16
B REGISTER
RESULT REGISTER
16
which is loaded along with the B
operands. The operands are specified
to be in two’s complement format
when TC is asserted and unsigned
magnitude when TC is deasserted.
Mixed mode operation is not allowed.
For two’s complement operands, the
17 most significant bits at the output
of the asynchronous multiplier array
are shifted one bit position to the left.
This is done to discard the redundant
copy of the sign-bit, which is in the
most significant bit position, and
extend the bit precision by one bit.
The result is then truncated to the 16
MSB’s and loaded into the output
register on the rising edge of CLK B.
The contents of the output register are
made available via three-state buffers
by asserting OE. When OE is de-
asserted, the outputs (R
23-8
) are in the
high impedance state.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LMU112 | 12 x 12-bit Parallel Multiplier |
| LMU112PC25 | 12 x 12-bit Parallel Multiplier |
| LMU112PC50 | 12 x 12-bit Parallel Multiplier |
| LMU216 | High-Speed, Low Power， 16-Bit Parallel Multiplier(高速，低功耗，16位并行乘法器) |
| LMU16 | 16 x 16-bit Parallel Multiplier |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LMU112JC60 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Multiplier |
| LMU112PC25 | 制造商:LOGIC 制造商全稱:LOGIC 功能描述:12 x 12-bit Parallel Multiplier |
| LMU112PC50 | 制造商:LOGIC 制造商全稱:LOGIC 功能描述:12 x 12-bit Parallel Multiplier |
| LMU112PC60 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Multiplier |
| LMU112PCR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
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