參數(shù)資料
型號: LMS8117ADTX-1.8
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 基準電壓源/電流源
英文描述: 1A Low-Dropout Linear Regulator
中文描述: 1.8 V FIXED POSITIVE LDO REGULATOR, 1.25 V DROPOUT, PSSO2
封裝: TO-252, 3 PIN
文件頁數(shù): 7/16頁
文件大小: 777K
代理商: LMS8117ADTX-1.8
Application Note
1.0 EXTERNAL CAPACITORS/STABILITY
1.1 Input Bypass Capacitor
An input capacitor is recommended. A 10μF tantalum on the
input is a suitable input bypassing for almost all applications.
1.2 Adjust Terminal Bypass Capacitor
The adjust terminal can be bypassed to ground with a by-
pass capacitor (C
ADJ
) to improve ripple rejection. This by-
pass capacitor prevents ripple from being amplified as the
output voltage is increased. At any ripple frequency, the
impedance of the C
ADJ
should be less than R1 to prevent the
ripple from being amplified:
1/(2
π
*f
RIPPLE
*C
ADJ
)
<
R1
The R1 is the resistor between the output and the adjust pin.
Its value is normally in the range of 100-200
. For example,
with R1 = 124
and f
RIPPLE
= 120Hz, the C
ADJ
should be
>
11μF.
1.3 Output Capacitor
The output capacitor is critical in maintaining regulator sta-
bility, and must meet the required conditions for both mini-
mum amount of capacitance and ESR (Equivalent Series
Resistance). The minimum output capacitance required by
the LMS8117A is 10μF, if a tantalum capacitor is used. Any
increase of the output capacitance will merely improve the
loop stability and transient response. The ESR of the output
capacitor should be greater than 0.5
and less than 5
. In
the case of the adjustable regulator, when the C
is used,
a larger output capacitance (22μf tantalum) is required.
2.0 OUTPUT VOLTAGE
The LMS8117A adjustable version develops a 1.25V refer-
ence voltage, V
REF
, between the output and the adjust ter-
minal. As shown in
Figure 1
, this voltage is applied across
resistor R1 to generate a constant current I1. The current
I
ADJ
from the adjust terminal could introduce error to the
output. But since it is very small (60μA) compared with the I1
and very constant with line and load changes, the error can
be ignored. The constant current I1 then flows through the
output set resistor R2 and sets the output voltage to the
desired level.
For fixed voltage devices, R1 and R2 are integrated inside
the devices.
For fixed voltage devices, R1 and R2 are integrated inside
the devices.
3.0 LOAD REGULATION
The LMS8117A regulates the voltage that appears between
its output and ground pins, or between its output and adjust
pins. In some cases, line resistances can introduce errors to
the voltage across the load. To obtain the best load regula-
tion, a few precautions are needed.
Figure 2
, shows a typical application using a fixed output
regulator. The Rt1 and Rt2 are the line resistances. It is
obvious that the V
is less than the V
by the sum of
the voltage drops along the line resistances. In this case, the
load regulation seen at the R
would be degraded from
the data sheet specification. To improve this, the load should
be tied directly to the output terminal on the positive side and
directly tied to the ground terminal on the negative side.
10119617
FIGURE 1. Basic Adjustable Regulator
10119618
FIGURE 2. Typical Application using Fixed Output
Regulator
L
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