參數(shù)資料
型號(hào): LMP90078MHX/NOPB
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類(lèi): 模擬信號(hào)調(diào)理
英文描述: SPECIALTY ANALOG CIRCUIT, PDSO28
封裝: LEAD FREE, PLASTIC, MO-153, TSSOP-28
文件頁(yè)數(shù): 28/62頁(yè)
文件大?。?/td> 1721K
代理商: LMP90078MHX/NOPB
30169732
FIGURE 22. DrdybCase1 Connection Diagram
As shown in Figure 22, the drdyb signal and SDO can be
multiplexed on the same pin as their functions are mostly
complementary. In fact, this is the default mode for the
SDO/DRDYB pin.
Figure 23 shows a timing protocol for DrdybCase1. In this
case, start by asserting CSB first to monitor a drdyb assertion.
When the drdyb signal asserts, begin writing the Instruction
Bytes (INST1, UAB, INST2) to read from or write to registers.
Note that INST1 and UAB are omitted from the figure below
because this transaction is only required if a new UAB needs
to be implemented.
While the CSB is asserted, DRDYB is driving the
SDO/DRDYB pin unless the device is reading data, in which
case, SDO will be driving the pin. If CSB is deasserted, then
the SDO/DRDYB pin is High-Z.
30169701
FIGURE 23. Timing Protocol for DrdybCase1
DrdybCase2:
Combining
SDO/DRDYB
with
SDO_DRDYB_DRIVER = 0x03
SDO/DRDYB can be made independent of CSB by setting
SDO_DRDYB_DRIVER = 0x03 in the SPI Handshake Control
register. In this case, DRDYB will drive the pin unless the de-
vice is reading data, independent of the state of CSB. SDO
will drive the pin when CSB is asserted and the device is
reading data.
With this scheme, one can use SDO/DRDYB as a true inter-
rupt source, independent of the state of CSB. But this scheme
can only be used when the LMP900xx is the only device con-
nected to the master's SPI bus because the SDO/DRDYB pin
will be DRDYB even when CSB is deasserted.
The timing protocol for this case can be seen in Figure 24.
When drdyb asserts, assert CSB to start the SPI transaction
and begin writing the Instruction Bytes (INST1, UAB, INST2)
to read from or write to registers.
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LMP90080/LMP90079/LMP90078/LMP90077
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