參數(shù)資料
型號(hào)： LMP90078MH/NOPB
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 模擬信號(hào)調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, PDSO28
封裝： LEAD FREE, PLASTIC, MO-153, TSSOP-28
文件頁(yè)數(shù)： 27/62頁(yè)
文件大?。?/td> 1721K
代理商： LMP90078MH/NOPB
16.5.4 CSB - Chip Select Bar
An SPI transaction begins when the master asserts (active
low) CSB and ends when the master deasserts (active high)
CSB. Each transaction might be separated by a subsequent
one with a CSB deassertion, but this is optional. Once CSB
is asserted, it must not pulse (deassert and assert again) dur-
ing a (desired) transaction.
CSB can be grounded in systems where LMP900xx is the only
SPI slave. This frees the software from handling the CSB.
Care has to be taken to avoid any false edge on SCLK, and
while operating in this mode, the streaming transaction should
not be used because exiting from this mode can only be done
through a CSB deassertion.
16.5.5 SPI Reset
SPI Reset resets the SPI-Protocol State Machine by moni-
toring the SDI for at least 73 consecutive 1's at each SCLK
rising edge. After an SPI Reset, SDI is monitored for a pos-
sible Write Instruction at each SCLK rising edge.
SPI Reset will reset the Upper Address Register (URA) to 0,
but the register contents are not reset.
By default, SPI reset is disabled, but it can be enabled by
writing 0x01 to SPI Reset Register (ADDR 0x02).
16.5.6 DRDYB - Data Ready Bar
DRDYB is a signal generated by the LMP900xx that indicates
a fresh conversion data is available in the ADC_DOUT reg-
isters.
DRDYB is automatically asserted every (1/ODR) second as
seen in Figure 20. Before the next assertion, DRDYB will
pulse for t
DRDYB second. The value for tDRDYB can be found in
30169785
FIGURE 20. DRDYB Behavior
If ADC_DOUT is being read while a new ADC_DOUT be-
comes available, then the ADC_DOUT that is being read is
still valid (Figure 21). DRDYB will still be deasserted every 1/
ODR second, but a consecutive read on the ADC_DOUT reg-
ister will fetch the newly converted data available.
30169712
FIGURE 21. DRDYB Behavior for an Incomplete ADC_DOUT Reading
DRDYB can also be accessed via registers using the
DT_AVAIL_B bit. This bit indicates when fresh conversion
data is available in the ADC_DOUT registers. If new conver-
sion data is available, then DT_AVAIL_B = 0; otherwise,
DT_AVAIL_B = 1.
A complete reading for DT_AVAIL_B occurs when the MSB
of ADC_DOUTH is read out. This bit cannot be reset even if
REG_AND_CNV_RST = 0xC3.
DrdybCase1:
Combining
SDO/DRDYB
with
SDO_DRDYB_DRIVER = 0x00
33
www.national.com
LMP90080/LMP90079/LMP90078/LMP90077
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LMP90078MHX/NOPB 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
LMP90079 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Sensor AFE System: Multi-Channel, Low-Power 16-Bit
LMP90079MH/NOPB 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
LMP90079MHE/NOPB 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
LMP90079MHX/NOPB 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
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