RIN 50: - V +
參數(shù)資料
型號: LMH6734MQX/NOPB
廠商: National Semiconductor
文件頁數(shù): 9/21頁
文件大?。?/td> 0K
描述: IC BUFFER TRPL SELECT 16-SSOP
標(biāo)準(zhǔn)包裝: 2,500
系列: PowerWise®
應(yīng)用: 電流反饋
電路數(shù): 3
-3db帶寬: 925MHz
轉(zhuǎn)換速率: 3750 V/µs
電流 - 電源: 19.5mA
電流 - 輸出 / 通道: 80mA
電壓 - 電源,單路/雙路(±): 3 V ~ 12 V,±1.5 V ~ 6 V
安裝類型: 表面貼裝
封裝/外殼: 16-LSSOP(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 16-QSOP
包裝: 帶卷 (TR)
配用: LMH730275/NOPB-ND - EVAL BOARD HS TRIPLE SSOP OPAMP
其它名稱: LMH6734MQX
+
-
RIN
50:
- V
+ V
ROUT
50:
CL
10 pF
RL
1 k:
VIN
0.1
10
FREQUENCY (MHz)
-20
-12
0
N
O
R
MAL
IZ
ED
G
AI
N
(
d
B
)
1000
100
1
-4
-8
-16
-2
-6
-10
-14
-18
L = 10 ft
L = 25 ft
L = 50 ft
L = 100 ft
L = 150 ft
L = 200 ft
V
+
= +5V
V
-
= -5V
VIN = 1 VPP
CAT5 LENGTH = L
OBSOLETE
SNOSAY0C – JUNE 2007 – REVISED APRIL 2013
Figure 46. Frequency Response vs. Normalized Gain and CAT5 Cable Length
DRIVING CAPACITIVE LOADS
Capacitive output loading applications will benefit from the use of a series output resistor ROUT. Figure 47 shows
the use of a series output resistor, ROUT, to stabilize the amplifier output under capacitive loading. Capacitive
loads of 5 to 120 pF are the most critical, causing ringing, frequency response peaking and possible oscillation.
The charts “Suggested ROUT vs. Cap Load” give a recommended value for selecting a series output resistor for
mitigating capacitive loads. The values suggested in the charts are selected for 0.5 dB or less of peaking in the
frequency response. This gives a good compromise between settling time and bandwidth. For applications where
maximum frequency response is needed and some peaking is tolerable, the value of ROUT can be reduced
slightly from the recommended values.
Figure 47. Decoupling Capacitive Loads
LAYOUT CONSIDERATIONS
Whenever questions about layout arise, use the evaluation board as a guide. The LMH730275 is the evaluation
board supplied with samples of the LMH6734.
To reduce parasitic capacitances, ground and power planes should be removed near the input and output pins.
For long signal paths controlled impedance lines should be used, along with impedance matching elements at
both ends.
Bypass capacitors should be placed as close to the device as possible. Bypass capacitors from each rail to
ground are applied in pairs. The larger electrolytic bypass capacitors can be located farther from the device, the
smaller ceramic capacitors should be placed as close to the device as possible. The LMH6734 has multiple
power and ground pins for enhanced supply bypassing. Every pin should ideally have a separate bypass
capacitor. Sharing bypass capacitors may slightly degrade second order harmonic performance, especially if the
supply traces are thin and /or long. In Figure 35, Figure 36, and Figure 37 it is recommended an optional
capacitor, CSS= 0.01 μF, be connected between the split supplies for best second harmonic distortion. Another
option to using CSS is to use pairs of 0.01 μF and 0.1 μF ceramic capacitors for each supply bypass.
Copyright 2007–2013, Texas Instruments Incorporated
17
Product Folder Links: LMH6734
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