VCC 10 k: 5 k: 80: VCC 10 k: LMH0002 www.ti.co" />
參數(shù)資料
型號(hào): LMH0002TMA/NOPB
廠商: National Semiconductor
文件頁數(shù): 9/13頁
文件大小: 0K
描述: IC CABLE DRIVER DGTL 8-SOIC
標(biāo)準(zhǔn)包裝: 95
類型: 串行驅(qū)動(dòng)器
應(yīng)用: SMPTE 259M / 344M
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SOIC
包裝: 管件
產(chǎn)品目錄頁面: 1278 (CN2011-ZH PDF)
配用: SD002EVK-ND - BOARD EVALUATION LMH0002
其它名稱: *LMH0002TMA
*LMH0002TMA/NOPB
LMH0002TMA
10 k:
SDI
VCC
10 k:
5 k:
80:
VCC
10 k:
SNLS215E – JANUARY 2006 – REVISED APRIL 2013
APPLICATION INFORMATION
Device Operation
INPUT INTERFACING
The LMH0002 accepts either differential or single-ended input. The inputs are self-biased, allowing for simple AC
or DC coupling. DC-coupled inputs must be kept within the specified common-mode range. SDI and SDI are self-
biased at approximately 2.1V with VCC = 3.3V. Figure 3 shows the differential input stage for SDI and SDI.
Figure 3. Differential Input Stage for SDI and SDI.
OUTPUT INTERFACING
The LMH0002 uses current mode outputs. Single-ended output levels are 800 mVP-P into 75 AC-coupled
coaxial cable (with RREF = 750). Output level is controlled by the value of the RREF resistor connected between
the RREF pin and VCC.
The RREF resistor should be placed as close as possible to the RREF pin. In addition, the copper in the plane
layers below the RREF network should be removed to minimize parasitic capacitance.
OUTPUT SLEW RATE CONTROL
The LMH0002 output rise and fall times are selectable for either SMPTE 259M or SMPTE 292M compliance via
the SD/HD pin. For slower rise and fall times, or SMPTE 259M compliance, SD/HD is set high. For faster rise
and fall times, or SMPTE 292M compliance, SD/HD is set low.
REPLACING THE GENNUM GS1528, GS1528A, and GS1578A
The LMH0002MA is form-fit-function compatible with the Gennum GS1528 and GS1528A. The LMH0002SQ is
form-fit-function compatible with the Gennum GS1578A.
Copyright 2006–2013, Texas Instruments Incorporated
5
Product Folder Links: LMH0002
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