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參數(shù)資料
| 型號(hào)： | LMC835VX |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 音頻控制 |
| 英文描述： | 1 CHANNEL(S), EQUALIZER CIRCUIT, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁(yè)數(shù)： | 6/18頁(yè) |
| 文件大?。?/td> | 474K |
| 代理商： | LMC835VX |
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Typical Applications (Continued)
Sample Subroutine Program for
Figure 14 LMC835-COP404L CPU Interface
HEX
CODE
LABEL
MNEMONICS
COMMENTS
3F
LMC835
LBI
3F
POINT TO RAMADDRESS 3F
05
SEND
LD
RAMDATA TO A
22
SC
SET CARRY
335F
OGI
SET PORT G
4 1111 OPEN THE AND GATES
4F
XAS
SWAP A AND SIO
CLOCK START
05
LD
RAMDATA TO A
MAKE SURE A
4 DATA
07
XDS
SWAP A AND RAMDATA
RAMADDRESS
4RAMADDRESS11
05
LD
RAMDATA TO A
4F
XAS
SWAP A AND SIO
05
LD
RAMDATA TO A
MAKE SURE A
4NEWDATA
07
XDS
SWAP A AND RAMDATA
RAMADDRESS
4RAMADDRESS11
32
RC
RESET CARRY
4F
XAS
SWAP A AND SIO
CLOCK STOP
335D
OGJ
13
SET PORT G
41101 MAKE STROBE LOW
335B
OGI
11
SET PORT G
41011 MAKE STROBE HIGH CLOSE THE
GATES
4E
CBA
BD TO A
43
AISC
3
RAMADDRESSk3C THEN RETURN
48
RET
80
JP
SEND
RAM
ADDRESS
COMMENTS
3C
DATA
GAIN DATA D4
1D7
3D
DATA
GAIN DATA D0
1D3
3E
DATA
BAND DATA D4
1D7
3F
DATA
BAND DATA D0
1D3
Application Hints
SWITCHING NOISE
The LMC835 uses CMOS analog switches that have small
leakages (less than 50 nA) When a band is selected for flat
gain all the switches in that band are open and the resona-
tor circuit is not connected to the LMC835 resistor network
It is only in the flat mode that the small leakage currents can
cause problems The input to the resonator circuit is usually
a capacitor and the leakage currents will slowly charge up
this capacitor to a large voltage if there is no resistive path
to limit it When the band is set to any value other than flat
the charge on the capacitor will be discharged by the resis-
tor network and there will be a transient at the output To
limit the size of this transient RLEAK is necessary
HOW TO AVOID SWITCHING NOISE DUE TO LEAKAGE
CURRENT
(Refer to
Figures 7 and 8 )
To avoid switching noise due to leakage currents when
changing the gain it is recommended to put RLEAKe 100
kX between Pin 3 and Pin 511 each Pin 26 and Pin 12
24 each The resistor limits the voltage that the capacitor
can charge to with minimal effects on the equalization The
frequency response change due to RLEAK are shown in Fig-
ure 15 The gain error is only 02 dB and Q error is only 5%
at 12 dB boost or cut
SIMPLE WORD GENERATOR
(Figure 6)
Circuit operation revolves around an MM74HC165 parallel-
inserial-out shift register Data bits D0 through D7 are ap-
plied to the parallel of the MM74HC165 from 8 toggle
switches The bits are shifted out to the DATA input of the
LMC835 in sync with the clock When all data bits have
been loaded CLOCK is inhibited and a STROBE pulse is
generated this sequence is initiated by a START pulse
LMC835-COP404L CPU INTERFACE
(Refer to
Figure 14 )
The diagram shows AND gates between the COP and the
LMC835 These permit G2 to inhibit the CLOCK and DATA
lines (SK and SO) during a STROBE (G1) pulse This func-
tion may also be implemented in software As shown in
Fig-
ure 2 the data groups are shifted in D0 first Data is loaded
on positive clock edges
POWER SUPPLIES
These applications show LM317337 regulators for the
g
75V supplies for the LMC835 Since the latter draws only
5 mA max 1k series dropping resistors from the g15V op
amp supply and a pair of 75V zeners and bypass caps will
also suffice
14
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