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| 型號(hào)： | LMC7101BIM5 |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類(lèi)： | 運(yùn)算放大器 |
| 英文描述： | Tiny Low Power Operational Amplifier with Rail-To-Rail Input and Output |
| 中文描述： | OP-AMP, 9000 uV OFFSET-MAX, 0.6 MHz BAND WIDTH, PDSO5 |
| 封裝： | SOT-23, 5 PIN |
| 文件頁(yè)數(shù)： | 15/18頁(yè) |
| 文件大小： | 853K |
| 代理商： | LMC7101BIM5 |
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4.0 Capacitive Load Tolerance
(Continued)
nation of the op-amp’s output impedance and the capacitive
load induces phase lag. This results in either an under-
damped pulse response or oscillation.
Capacitive load compensation can be accomplished using
resistive isolation as shown in Figure 4 This simple tech-
nique is useful for isolating the capacitive input of multiplex-
ers and A/D converters.
5.0 Compensating for Input
Capacitance when Using Large
Value Feedback Resistors
When using very large value feedback resistors, (usually
>
500 k
) the large feed back resistance can react with the
input capacitance due to transducers, photodiodes, and cir-
cuit board parasitics to reduce phase margins.
The effect of input capacitance can be compensated for by
adding a feedback capacitor. The feedback capacitor (as in
Figure 5), C
f
is first estimated by:
or
R
1
C
IN
≤
R
2
C
f
which typically provides significant overcompensation.
Printed circuit board stray capacitance may be larger or
smaller than that of a breadboard, so the actual optimum
value for C
may be different. The values of C
should be
checked on the actual circuit. (Refer to the LMC660 quad
CMOS amplifier data sheet for a more detailed discussion.)
DS011991-11
FIGURE 4. Resistive Isolation
of a 330 pF Capacitive Load
DS011991-12
FIGURE 5. Cancelling the Effect of Input Capacitance
www.national.com
15
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