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參數(shù)資料
| 型號(hào)： | LMC6442IMX |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | CAP, 0.1UF 50V CERM CHIP, 0805 Z5U |
| 中文描述： | DUAL OP-AMP, 8000 uV OFFSET-MAX, 0.0095 MHz BAND WIDTH, PDSO8 |
| 封裝： | 0.150 INCH, PLASTIC, SOIC-8 |
| 文件頁(yè)數(shù)： | 11/15頁(yè) |
| 文件大?。?/td> | 553K |
| 代理商： | LMC6442IMX |
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Application Notes
(Continued)
For convenience, Fig. 3 shows R1 vs R
F
for different values
of R.
Design Considerations for Capacitive Loads:
As with
many other opamps, the LMC6442 is more stable at higher
closed loop gains when driving a capacitive load. Figure 4
shows minimum closed loop gain versus load capacitance,
to achieve less than 10% overshoot in the output small sig-
nal response. In addition, the LMC6442 is more stable when
it provides more output current to the load and when its out-
put voltage does not swing close to V
.
The LMC6442 is more tolerant to capacitive loads when the
equivalent output load resistance is lowered or when output
voltage is 1V or greater from the V
supply. The capacitive
load drive capability is also improved by adding an isolating
resistor in series with the load and the output of the device.
Figure 5 shows the value of this resistor for various capaci-
tive loads (A
V
= 1), while limiting the output to less than 10
% overshoot.
Referring to the Typical Performance Characteristics plot of
Phase Margin (Worst Case) vs Supply Voltage, note that
Phase Margin increases as the equivalent output load resis-
tance is lowered. This plot shows the expected Phase Mar-
gin when the device output is very close to V
, which is the
least stable condition of operation. Comparing this Phase
Margin value to the one read off the Open Loop Gain/Phase
vs Frequency plot, one can predict the improvement in
Phase Margin if the output does not swing close to V
. This
dependence of Phase Margin on output voltage is minimized
as long as the output load, R
L
, is about 1M
or less.
Output Phase Reversal:
The LMC6442 is immune against
this behavior even when the input voltages exceed the com-
mon mode voltage range.
Output Time Delay:
Due to the ultra low power consump-
tion of the device, there could be as long as 2.5 ms of time
delay from when power is applied to when the device output
reaches its final value.
DS100064-47
FIGURE 4. Minimum Operating Gain vs Capactive Load
DS100064-43
FIGURE 5. Isolating Resistor Value vs Capactive Load
www.national.com
11
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| LMC6442IMX/NOPB | 功能描述:運(yùn)算放大器 - 運(yùn)放 RoHS:否 制造商:STMicroelectronics 通道數(shù)量:4 共模抑制比（最小值）:63 dB 輸入補(bǔ)償電壓:1 mV 輸入偏流（最大值）:10 pA 工作電源電壓:2.7 V to 5.5 V 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-16 轉(zhuǎn)換速度:0.89 V/us 關(guān)閉:No 輸出電流:55 mA 最大工作溫度:+ 125 C 封裝:Reel |
| LMC6442IN | 功能描述:運(yùn)算放大器 - 運(yùn)放 RoHS:否 制造商:STMicroelectronics 通道數(shù)量:4 共模抑制比（最小值）:63 dB 輸入補(bǔ)償電壓:1 mV 輸入偏流（最大值）:10 pA 工作電源電壓:2.7 V to 5.5 V 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-16 轉(zhuǎn)換速度:0.89 V/us 關(guān)閉:No 輸出電流:55 mA 最大工作溫度:+ 125 C 封裝:Reel |
| LMC6442IN/NOPB | 功能描述:運(yùn)算放大器 - 運(yùn)放 Dual Rro Micropwr Op Amp RoHS:否 制造商:STMicroelectronics 通道數(shù)量:4 共模抑制比（最小值）:63 dB 輸入補(bǔ)償電壓:1 mV 輸入偏流（最大值）:10 pA 工作電源電壓:2.7 V to 5.5 V 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-16 轉(zhuǎn)換速度:0.89 V/us 關(guān)閉:No 輸出電流:55 mA 最大工作溫度:+ 125 C 封裝:Reel |
| LMC6442INNOPB | 制造商:National Semiconductor 功能描述:OP Amp Dual GP R-R O/P 10V 8-Pin PDIP Rail |
| LMC6462 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Micropower, Rail-to-Rail Input and Output CMOS Operational Amplifier |
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