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參數(shù)資料
| 型號： | LMC2626IM |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 模擬信號調理 |
| 英文描述： | CMOS LDOR/Buffer Chip for Row Inversion Flat Panel Display Systems |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDSO8 |
| 封裝： | 0.150 INCH, PLASTIC, SOP-8 |
| 文件頁數(shù)： | 1/6頁 |
| 文件大?。?/td> | 92K |
| 代理商： | LMC2626IM |
TL/H/12541
L
PRELIMINARY
November 1995
LMC2626
CMOS LDOR/Buffer Chip for Row
Inversion Flat Panel Display Systems
General Description
The LMC2626 integrated circuit is specifically developed for
a row inversion TFT FPD system architecture. It is designed
only to be used in conjunction with National’s LM2625
switching regulator chip.
Built on National’s advanced CMOS CS80 process, this chip
generates a high-power, precision square-wave from a digi-
tal sync signal. The chip also contains thermal shutdown
circuitry, system shutdown circuitry, and a low drop-out volt-
age regulator to generate a 4.2 volt supply from an external-
ly applied reference voltage of 1.227V.
Features
Y
Used in conjunction with LM2625 chip
Y
High output current buffer
Y
Low buffer on resistance
Y
System shutdown control
Y
LDO voltage regulator
Y
LDOR dropout 0.3V maximum at 150 mA
Y
Thermal shutdown/short circuit protection
Y
External reference required for LDOR
Y
V
REF
pin converts to a digital pin to shutdown LM2625
Connection Diagram
8-Pin SO
TL/H/12541–1
Top View
Pin Description
Pin
Y
Pin Name
Description
1
V
REF
1.218V to 1.242V Ext. Reference
from LM2625 (see Note 8)
2
SD
System Shutdown input pin for
LMC2626 and LMC2625
3
SYNC
Digital input square wave from FPD
controller
4
GND
Ground
5
P5V
Precision Regulated
a
5V Supply
6
V
OUT
Power Buffer Output
7
V
IN
FPD System Supply (
a
4.5V to
a
5.5V)
8
V
SH
Low Drop-Out Voltage Regulator
Output
Ordering Information
Package
Temperature Range
b
40
§
C to
a
85
§
C
NSC
Drawing
Transport
Media
8-Pin SO
LMC2626IM
M08A
Rail
Tape and
Reel
C
1996 National Semiconductor Corporation
RRD-B30M26/Printed in U. S. A.
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