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參數(shù)資料
| 型號： | LM98503 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 10-Bit, 18 MSPS Camera Signal Processor |
| 中文描述： | 10位，18 MSPS的攝像機信號處理器 |
| 文件頁數(shù)： | 21/25頁 |
| 文件大?。?/td> | 203K |
| 代理商： | LM98503 |
www.national.com
21
Serial Interface Read/Write Description
1.0 Writing to the Serial Registers
To write to the serial registers, the timing diagram shown in
Figure 13 must be met. First CE is toggled low. SI DATA may
then be clocked in, and the data present on the rising edge of
the serial clock is loaded in. The data continues to be clocked in,
until CE toggles high. The data present in the register is the last
13 bits of data sent before CE toggled high. Therefore, for
example, if 20 bits were sent when CE was toggled low, the first
7 bits were discarded, and the data loaded are the remaining 13
bits. As seen in Figure 13, these 13 bits are composed of 8 data
bits, 4 address bits, and 1 read/write bit. When writing to the
registers, the read/write bit must be low. When CE toggles high,
the register is written to, and the LM98503 now functions with
this new data.
2.0 Reading the Serial Registers
To read the serial registers, the timing diagram shown in Figure
12 must be met. When CE is toggled low, and data is loaded as
described above in the writing sequence. When CE toggles
high, the new 13 bit word is considered, except this time the
read/write bit should be a 1 indicating a read. The 8 data bits are
not considered, but act only as place holders. When CE toggles
low again, the data that resides at the address considered in the
previous read or write routine, begins clocking out SO DATA.
The data streams out MSB-LSB as shown in Figure 12. Whether
a read or a write was invoked in the previous sequence, the SO
DATA will clock out the contents of the address considered in
the previous sequence.
L
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| LM98503CCVV | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:10-Bit, 18 MSPS Camera Signal Processor |
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