參數(shù)資料
型號: LM98501
廠商: National Semiconductor Corporation
英文描述: 10-Bit, 27 MSPS Camera Signal Processor
中文描述: 10位,27 MSPS的攝像機信號處理器
文件頁數(shù): 12/24頁
文件大?。?/td> 490K
代理商: LM98501
CDS Sampling Timing
Horizontal Interval Timing
DS101292-5
1
SHP overrides the CLAMP signal’s falling edge for sampling the reset voltage (SHP is active-low by default).
2
The CLAMP signal is an internal signal derived from the CLK input whose falling edge samples the CCD reset voltage by default.
FIGURE 4. Pixel Rate Reset Voltage Sampling
DS101292-6
1
SHP overrides the CLAMP signal’s falling edge for sampling the reset voltage (SHD is active-low by default).
2
The SAMPLE signal is an internal signal derived from the CLK input whose falling edge samples the CCD video signal by default.
FIGURE 5. Pixel Rate Video Signal Sampling
DS101292-7
FIGURE 6. Typical Horizontal Interval Timing
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