參數資料
型號: LM9830VJD
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 消費家電
英文描述: EuroDOCSIS 2.0 Diplexer Filter w/surge protection
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝: PLASTIC, TQFP-100
文件頁數: 38/45頁
文件大?。?/td> 566K
代理商: LM9830VJD
38
http://www.national.com
line rate, the output would be:
R
1
, G
1
, B
1
, R
2
, G
2
, B
2
,..., R
n-1
, G
n-1
, B
n-1
, R
n
, G
n
, B
n
with the Red data representing line m, the Green data represent-
ing line m-x, and the Blue data representing line m-2x.
The length of a line of image data sent to the PC depends on sev-
eral factors:
The number of physical pixels in the sensor, equal to (1 + Valid
Pixel End - Valid Pixel Start), which we will call Valid Pixels,
The horizontal resolution set in the configuration register,
The pixel depth (1, 2, 4, or 8 bits), and
When scanning with the horizontal resolution equal to the optical
resolution (300dpi or 600dpi) at an 8 bit pixel depth, the number
of bytes in a line is equal to the number of Valid Pixels (or three
times the number of Valid Pixels, if R, G, and B are interleaved).
If the horizontal resolution is set to a number below the optical
resolution, the number of bytes in a line is equal to:
Valid Pixels----------------------------------------------------
=
If the pixel depth is reduced from 8 to 4, 2, or 1 bits, the bytes per
line will also decrease:
Valid Pixels---------------------------------------------------------------------------
=
since multiple pixels are being packed into one byte. For a 4 bit
pixel, there are 2 pixels/byte, for a 2 bit pixel, there are 4 pix-
els/byte, and for a 1 bit pixel, there are 8 pixels/byte.
The scanner software on the host must strip the status byte from
the end of each line before reconstructing the image.
8.2.1 Reconstructing 12 bit Image Data Received By the PC
The 12 bit Data Mode is a special one for the LM9830. In the 12
bit Data Mode the horizontal resolution is always equal to the
optical resolution, the gamma correction is bypassed, and the
Pixel Packing stage is bypassed.
Each pixel is stored in the SRAM and transmitted to the PC in two
bytes, a high byte containing the 4 bit MSB of the pixel (format 0 0
0 0 B11 B10 B9 B8), and a low byte containing the 8 bit LSB.
This mode is used to acquire 12 bit data for accurate gain and off-
set calibration, and for applications requiring maximum resolution
data without gamma correction.
8.3 High Speed Forward
When register 07 is set to a 1, the LM9830 moves the motor for-
ward at maximum speed (determined by the fast feed stepsize,
registers 48 and 49) until either one of the Paper Sensor inputs
becomes True (if that sensor has been properly programmed to
interrupt scanner movement). Paper Sensor #2 can be used to
cause a delayed stop. If the
FullSteps to Scan after Paper Sen-
sor #2 trips
register is greater than 0, motor movement will con-
tinue for the programmed number of full steps. This can be used
to eject paper in sheetfed scanners.
8.4 High Speed Reverse
When register 07 is set to a 2, the LM9830 moves the motor
backwards at maximum speed (determined by the fast feed step-
size, registers 48 and 49) until either one of the Paper Sensor
inputs becomes True (if that sensor has been properly pro-
grammed to interrupt scanner movement). The
FullSteps to
Scan after Paper Sensor #2 trips
register is not used in the
High Speed Reverse mode. This function is generally used to
home the sensor in flatbed scanning applications.
8.5 Short Example of a Scan
PC sends Daisy Chain Protocol Sequence to take the LM9830
out of Transparent mode.
The LM9830 responds and shuts off printer
PC writes to Configuration Register establishing EPP or Nibble
Mode for sending data from the LM9830 to PC
PC configures the LM9830 by writing to the configuration regis-
ters
If no calibration data for the scanner is found in the PC, or if the
user has requested a new calibration, the PC has the LM9830
scan a calibration image, then calculates the calibration coeffi-
cients for the scanner.
PC transmits the calibration information to the LM9830 (this
step can be skipped if power to the LM9830 has been main-
tained since the last time the calibration data was sent).
If a sheetfed, the PC now polls the LM9830 status registers to
see if there is any paper inserted. If a flatbed, it moves the scan
head to the home position.
The PC sets the Scanning bit in the Configuration Register.
The PC sends a series of reads to the LM9830 (Figures 60-62)
and gets a byte of pixel data for each read. The PC should be
keeping track of exactly how many bytes there will be in an
image and simply receive data until then, but the capability
exists for it to read from any Configuration Register at this time,
including the status bits for the 4 multipurpose inputs (paper
sensors, user buttons, etc.) and the number of image data bytes
available in the buffer. The PC can also write to any register,
including the register containing the Scanning bit. If this bit is
cleared, the scan is aborted.
PC reads data until scan is complete or aborted.
PC writes to Configuration Register and clears Scanning bit.
If this is a flatbed scanner, the PC should now send a “return to
start of page” command. For a sheetfeeder, it can send a “fast
forward to end of page” command if needed.
Turn off the lights, complete any other shutdown activities.
PC sends command to put the LM9830 back in Transparent
mode.
9.0 Master Clock Source
The timing for the entire chip comes from the CRYSTAL OUT pin.
This clock is immediately divided down by the MCLK divider (reg-
ister 08), and the divided output is MCLK (Master CLOCK). The
MCLK divider range is from 1.0 to 32.5 in steps of 0.5. A configu-
ration register code of 0 divides the clock by 1.0, while a code of
63 divides the clock by 32.5. With a 48MHz crystal, this provides
an MCLCK range of 1.48MHz to 48MHz and a corresponding
ADC conversion rate of 184kHz to 6.00MHz. This divider can be
used to closely match the output data rate to the PC’s input data
rate, minimizing scan time.
MCLK is used to clock the vast majority of the LM9830’s circuits.
CRYSTAL OUT is used in a few subsections where the highest
possible clock speed is required (such as the PWM pulse genera-
Bytes/Line
Bytes/Line
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