
AC Electrical Characteristics
(Continued)
The following specifications apply for AGND = DGND = 0V, V
A
= V
D
= +5.0V
, f
= 24 MHz, t
MCLK
= 1/f
MCLK
,
t
r
= t
f
= 5 ns, R
s
= 25
.
Boldface limits apply for T
A
= T
J
= T
MIN
to T
MAX
; all other limits T
A
= T
J
Symbol
Parameter
Conditions
Typical
(Note 9)
50
Limits
(Note 10)
Units
(Limits)
ns (min)
ns (min)
t
SampHi
t
SampSU
High Time for SampCLK
SampCLK Falling Edge before Rising
Edge of MCLK
Falling Edge of MCLK before New Valid
Data
Hold Time of Current Data from Falling
edge of MCLK
D2(SCLK) Serial Clock Period
Input Data Setup Time before
D2(SCLK) Rising Edge
Input Data Hold Time after
D2(SCLK) Rising Edge
D2(SCLK) Rising Edge after Bit B0
before D1(Latch) Rising Edge
D1(Latch) Rising Edge before next
D2(SCLK) Rising Edge
High Time for D1(Latch)
D1(Latch) Rising Edge before
NewLine Falling Edge
4
t
DDO
40
ns (max)
t
HDO
15
ns (min)
f
SCLK
t
DSU
1
t
MCLK
(min)
0
ns (min)
t
DH
3
ns (min)
t
SCLKLA
3
ns (min)
t
LASCLK
3
ns (min)
t
LA
t
LANL
3
3
t
MCLK
(min)
t
SampCLK
(min)
Note 1:
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2:
All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified.
Note 3:
When the input voltage (V
IN
) at any pin exceeds the power supplies (V
IN
<
GND or V
IN
V
A
or V
D
), the current at that pin should be limited to 25 mA. The
50 mA maximum package input current rating limits the number of pins that can simultaneously safely exceed the power supplies with an input current of 25 mA to
two.
Note 4:
The maximum power dissipation must be derated at elevated temperatures and is dictated by T
Jmax
,
θ
JA
and the ambient temperature, T
A
. The maximum
allowable power dissipation at any temperature is P
D
= (T
Jmax
–T
A
)/
θ
JA
. T
Jmax
= 150C for this device. The typical thermal resistance (
θ
JA
) of this part when board
mounted is 84C/W for the M20 SOIC package.
Note 5:
Human body model, 100 pF capacitor discharged through a 1.5 k
resistor.
Note 6:
See AN450 “Surface Mounting Methods and Their Effect on Product Reliability” or the section titled “Surface Mount” found in any National Semiconductor
Linear Data Book for other methods of soldering surface mount devices.
Note 7:
Two diodes clamp the OS analog inputs to AGND and V
A
as shown below. This input protection, in combination with the external clamp capacitor and the
output impedance of the sensor, prevents damage to the LM9810/20 from transients during power-up.
Note 8:
To guarantee accuracy, it is required that V
A
and V
D
be connected together to the same power supply with separate bypass capacitors at each supply pin.
Note 9:
Typicals are at T
J
= T
A
= 25C, f
MCLK
= 24 MHz, and represent most likely parametric norm.
Note 10:
Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 11:
Integral non-linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that best fits the actual transfer function
of the ADC.
Note 12:
V
REF
is defined as the CCD OS voltage for the reference period following the reset feedthrough pulse. V
WHITE
is defined as the peak CCD pixel output
voltage for a white (full scale) image with respect to the reference level, V
. V
is defined as the peak positive deviation above V
of the reset feedthrough
pulse. The maximum correctable range of pixel-to-pixel V
variation is defined as the maximum variation in V
WHITE
(due to PRNU, light source intensity
variation, optics, etc.) that the LM9810/20 can correct for using its internal PGA.
DS100943-71
L
www.national.com
6