參數(shù)資料
型號： LM9822CCWMX
英文描述： Signal Conditioner
中文描述： 信號調(diào)理
文件頁數(shù)： 10/20頁
文件大?。?/td> 245K
代理商： LM9822CCWMX
Pin Descriptions
(Continued)
D1
D0
Input Mode
(NewLine
High)
D5-D3
D2 (SCLK)
D1 (Latch)
b7,
b6,
b7,
b6,
b1,
b0,
b1
b0
Don’t Care
Serial Data Clock.
Latch and Shift Enable Signal. When
D1(Latch) is low, data is shifted into
D0(SDI). When D1(Latch) goes high,
the last nine bits shifted into D0(SDI)
will be used to program the addressed
configuration register. To avoid
erroneous writes to the configuration
registers, D1(Latch) should be pulled
low when NewLine is high.
Serial Input Data. Data is valid on
D2(SCLK) rising edge. Three address
bits followed by six data bits (MSB first)
should be shifted into D0 before
D1(Latch) goes high.
D0 (SDI)
Timing Diagrams
DS100943-73
FIGURE 1. Pixel Conversion Timing and Latency
DS100943-74
FIGURE 2. SampCLK and Output Data Timing (NewLine Low)
L
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