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參數(shù)資料
| 型號(hào)： | LM9812 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | LM9812 30-Bit Color Linear CCD Sensor Processor |
| 中文描述： | LM9812 30位彩色線陣CCD傳感器處理器 |
| 文件頁數(shù)： | 30/37頁 |
| 文件大?。?/td> | 479K |
| 代理商： | LM9812 |
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EOC clock latency between the latching of the gain coefficient for
a particular pixel and the output of that pixel on the D0-D9 data-
bus.
Diagram 17 shows the case where the correction data (CD0-
CD9) is on the same bus as the output data (D0-D9) (Register 9,
bit 4=1). The LM9812 generates the GCLK signal only (Register
9, bit 5=1, bit 7=1). Gain correction data is latched on the rising
edge of GCLK, and offset correction data is latched on the falling
edge of GCLK. Using the EOC output to control the RD PIXEL
input allows the CD0-CD9 and the D0-D9 data to exist on the
same bus with no contention. There is a one EOC clock latency
between the latching of the gain coefficient for a particular pixel
and the output of that pixel on the D0-D9 databus.
In the previous modes of operation, the offset correction clock
(OCLK) and the gain (shading) correction clock (GCLK) are gen-
erated by the LM9812 and used to generate the RD pulses to
coefficient RAM. These clocks can also be configured as inputs
to allow compatibility with some existing ASICs or designs where
it is preferred to let the ASIC generate all the timing. The offset
data is always latched on the rising edge of OCLK. The gain data
is always latched on the rising edge of GCLK.
To operate the LM9812 with an externally supplied OCLK and
GCLK, set bit D7 of register 9 to a 0 and set the phase bit for
each clock. The procedure to determine the state of the phase bit
is described at the end of this section.
DIagrams 18 through 21 show the timing required when GCLK
and OCLK are configured as inputs to the LM9812 (Register 9, bit
5=0, bit 7=0). This option exists to allow the LM9812 to work with
ASICs designed for earlier systems, where the ASIC generates
the SRAM timing (instead of the LM9812). Diagrams 18 and 19
show the 2 bus mode (Register 9, bit 4=0), diagrams 20 and 21
show the 1 bus mode (Register 9, bit 4=1).
In these modes, GLCK and OCLK come from an external source
that may be asynchronous to the internally generated OCLK and
GCLK. While these clocks may be asynchronous, they will be the
same frequency, the ADC conversion rate (since offset and gain
coefficients are needed for every pixel, and the pixel data rate is
fixed by the ADC conversion rate).
The circuit shown in Figure 3 is implemented inside the LM9812
to synchronize (by delaying) the external coefficient clocks and
CD0-9 data with the internal LM9812 clocks.
CD0-9 data is always latched into register FF1 on the rising edge
of the external clock. The output of FF1 is then latched by FF2 on
the fallingedge of the external clock. So the latched data is avail-
able at the output of FF1 between the rising edges of the external
clock, and is valid at the output of FF2 between the falling edges
of the external clock. If the phase difference between the external
clock and EOC (the LM9812’s internal coefficient clock) is known,
then by selecting Q1 or Q2 as the input to FF3, the designer can
guarantee that the data will be valid on the rising edge of
GCLK
INT
, where it is latched into FF3 and synchronized to the
LM9812.
GCLK
INT
is not externally available to the user but it is basically
D
FF2
O
Q
Q
D
FF1
O
Q
Q
Ext OCLK
3:1
Mux
D
FF3
O
Q
Q
CD0-9
D
FF2
G
Q
Q
D
FF1
G
Q
Q
Ext GCLK
3:1
Mux
D
FF3
G
Q
Q
EOC
Latched
Offset
Correction
Data to
Offset Sub-
tractor
Latched
Gain
Correction
Data to
Multiplier
Internal OLCK
phase = 0°
phase = 180°
Internal GLCK
phase = 0°
phase = 180°
Figure 3: Using An External OCLK and GCLK
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| LM9812CCV | LM9812 30-Bit Color Linear CCD Sensor Processor |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LM9812CCV | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:LM9812 30-Bit Color Linear CCD Sensor Processor |
| LM981-SC36 | 功能描述:基本/快動(dòng)開關(guān) Foot Switch RoHS:否 制造商:Omron Electronics 觸點(diǎn)形式:SPDT 執(zhí)行器:Lever 電流額定值:5 A 電壓額定值 AC:250 V 電壓額定值 DC:30 V 功率額定值: 工作力:120 g IP 等級(jí):IP 67 NEMA 額定值: 端接類型:Wire 安裝:Panel |
| LM981-ZZ | 功能描述:基本/快動(dòng)開關(guān) Foot Switch RoHS:否 制造商:Omron Electronics 觸點(diǎn)形式:SPDT 執(zhí)行器:Lever 電流額定值:5 A 電壓額定值 AC:250 V 電壓額定值 DC:30 V 功率額定值: 工作力:120 g IP 等級(jí):IP 67 NEMA 額定值: 端接類型:Wire 安裝:Panel |
| LM981-ZZ-1 | 功能描述:基本/快動(dòng)開關(guān) Foot Switch RoHS:否 制造商:Omron Electronics 觸點(diǎn)形式:SPDT 執(zhí)行器:Lever 電流額定值:5 A 電壓額定值 AC:250 V 電壓額定值 DC:30 V 功率額定值: 工作力:120 g IP 等級(jí):IP 67 NEMA 額定值: 端接類型:Wire 安裝:Panel |
| LM9820 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
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