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參數(shù)資料
| 型號： | LM9801CCVF |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | Greyscale/24-Bit Color Linear CCD Sensor Processor |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PQFP52 |
| 封裝： | TQFP-52 |
| 文件頁數(shù)： | 27/34頁 |
| 文件大小： | 520K |
| 代理商： | LM9801CCVF |
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Applications Information
(Continued)
6.0 POWER SUPPLY CONSIDERATIONS
6.1 General
The LM9801 should be powered by a single
a
5V source
(unless 3V-compatible digital I/O is requiredDsee Section
6.2). The analog supplies (V
A
) and the digital supplies (V
D
and V
D(I/O)
) are brought out individually to allow separate
bypassing for each supply input. They should not be pow-
ered by two or more different supplies.
In systems with separate analog and digital
a
5V supplies,
all the supply pins of the LM9801 should be powered by the
analog
a
5V supply. Each supply input should be bypassed
to its respective ground with a 0.1
m
F capacitor located as
close as possible to the supply input pin. A single 10
m
F
tantalum capacitor should be placed near the V
A
supply pin
to provide low frequency bypassing.
To minimize noise, keep the LM9801 and all analog compo-
nents as far as possible from noise generators, such as
switching power supplies and high frequency digital busses.
If possible, isolate all the analog components and signals
(OS, reference inputs and outputs, V
A
, AGND) on an analog
ground plane, separate from the digital ground plane. The
two ground planes should be tied together at a single point,
preferably the point where the power supply enters the PCB.
6.2 3V Compatible Digital I/O
If 3V digital I/O operation is desired, the V
D(I/O)
pin may be
powered by a separate 3V
g
10% or 3.3V
g
10% supply.
In this case, all the digital I/O pins (CD0–CD7, CCLK,
MCLK, DD0–DD7, EOC, RD, SYNC, CS, SCLK, SDO, and
SDI) will be 3V compatible. The CCD clock signals (
w
1,
w
2,
RS, and TR) remain 5V outputs, powered by V
D
. In this case
the V
D(I/O)
input should be bypassed to DGND
(I/O)
with a
parallel combination of a 0.1
m
F capacitor and a 10
m
F tan-
talum capacitor.
6.3 Power Down Mode
Setting the Power Down bit to a ‘‘1’’ puts the device in a low
power standby mode. The CCD outputs (
w
1,
w
2, RS, and
TR) are pulled low and the analog sections are turned off to
conserve power. The digital logic will continue to operate if
MCLK continues and SYNC is held high, so for minimum
power dissipation MCLK should be stopped when the
LM9801 enters the Power Down mode. Recovery from Pow-
er Down typically takes 50
m
s (the time required for the
reference voltages to settle to 0.5 LSB accuracy).
7.0 COLOR
There are two primary ways to use the LM9801 in a color
system with a triple output (RGB) CCD. The first is to use
one LM9801 with an external multiplexer. This is the sim-
plest solution. The second technique is to use one LM9801
per RGB color.
7.1 Parallel Output CCD, One LM9801
Figure 12 is an example of how to use a single LM9801 with
a triple-output RGB CCD. In this case an entire line of red is
digitized, followed by an entire line of green, then blue. This
solution provides a 2.5 Mpixels/sec (for an effective 830k
RGB pixels/sec after de-interleaving) pixel rate using a high
performance triple output color CCD.
The Mux 1 multiplexer, located between the CCD’s OS out-
puts and the LM9801’s OS input, selects the color to be
digitized according to the states of the A and B inputs (de-
scribed below). The multiplexer’s speed requirements are
minimal because the mux switches at the line rate, not the
pixel rate. Also, since the output of the mux goes into a high
impedance, low-capacitance input, the ON resistance of the
mux is not critical. The 74HC4052 is a good choice for this
application.
TL/H/12814–39
FIGURE 12. Parallel Output CCD Application Circuit
http://www.national.com
27
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