
9.0 Pin Descriptions
Symbol
Pin #
Type
Function
PROCHOT
1
Digital I/O (Open-
Drain)
Connected to CPU1 PROCHOT (processor hot) signal through a
bidirectional level shifter. Supports TTL input logic levels and AGTL
compatible input logic levels.
GND
2
Ground
All grounds need to be tied together at the chip then taken to a low noise
system ground. A voltage difference between grounds may cause
erroneous results.
GND
3
Ground
All grounds need to be tied together at the chip then taken to a low noise
system ground. A voltage difference between grounds may cause
erroneous results.
GND
4
Ground
All grounds need to be tied together at the chip then taken to a low noise
system ground. A voltage difference between grounds may cause
erroneous results.
GND
5
Ground
All grounds need to be tied together at the chip then taken to a low noise
system ground. A voltage difference between grounds may cause
erroneous results.
GND
6
Ground
All grounds need to be tied together at the chip then taken to a low noise
system ground. A voltage difference between grounds may cause
erroneous results.
GPIO_0/TACH1
7
Digital I/O (Open-
Drain)
Can be configured as fan tach input or a general purpose open-drain digital
I/O.
GPIO_1/TACH2
8
Digital I/O (Open-
Drain)
Can be configured as fan tach input or a general purpose open-drain digital
I/O.
GPIO_2/TACH3
9
Digital I/O (Open-
Drain)
Can be configured as fan tach input or a general purpose open-drain digital
I/O.
GPIO_3/TACH4
10
Digital I/O (Open-
Drain)
Can be configured as fan tach input or a general purpose open-drain digital
I/O..
GPIO_4 / THERMTRIP 11
Digital I/O (Open-
Drain)
A general purpose open-drain digital I/O. Can be configured to monitor a
CPU's THERMTRIP signal to mask other errors. Supports TTL input logic
levels and AGTL compatible input logic levels.
GPIO_5
12
Digital I/O (Open-
Drain)
A general purpose open-drain digital I/O. Supports TTL input logic levels
and AGTL compatible input logic levels.
GPIO_6
13
Digital I/O (Open-
Drain)
Can be used to detect the state of CPU's IERR or a general purpose open-
drain digital I/O. Supports TTL input logic levels and AGTL compatible input
logic levels.
GPIO_7
14
Digital I/O (Open-
Drain)
A general purpose open-drain digital I/O. Supports TTL input logic levels
and AGTL compatible input logic levels.
VRD1_HOT
15
Digital Input
CPU1 voltage regulator HOT. Supports TTL input logic levels and AGTL
compatible input logic levels.
GND
16
Ground Input
All grounds need to be tied together at the chip then taken to a low noise
system ground. A voltage difference between grounds may cause
erroneous results.
VID6/GPI9
17
Digital Input
CPU VID6 input. Could also be used as a general purpose input to trigger
an error event. Supports TTL input logic levels and AGTL compatible input
logic levels.
SMBDAT
18
Digital I/O (Open-
Drain)
Bidirectional System Management Bus Data. Output configured as 5V
tolerant open-drain. SMBus 2.0 compliant.
SMBCLK
19
Digital Input
System Management Bus Clock. Driven by an open-drain output, and is 5V
tolerant. SMBus 2.0 Compliant.
ALERT/XtestOut
20
Digital Output (Open-
Drain)
Open-drain ALERT output used in an interrupt driven system to signal that
an error event has occurred. Masked error events do not activate the
ALERT output. When in XOR tree test mode, functions as XOR Tree output.
5
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