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參數(shù)資料
| 型號： | LM9617CCEA |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Monochrome CMOS Image Sensor VGA 30 FPS |
| 中文描述： | 單色CMOS圖像傳感器顯卡30醫(yī)科 |
| 文件頁數(shù)： | 20/37頁 |
| 文件大小： | 366K |
| 代理商： | LM9617CCEA |
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Functional Description
(continued)
14.0 DIGITAL VIDEO PORT
The captured image is placed onto a flexible 12-bit digital port as
shown in Figure 10. The digital video port consists of a program-
mable 12-bit digital Data Out Bus (
d[11:0]
) and three program-
mable synchronisation signals (
hsync, vsync, pclk
).
By default the synchronisation signals are configured to operate
in “
master”
mode. They can be programed to operate in “
slave
”
mode.
The following sections are a detailed description of the timing
and programming modes of digital video port.
Pixel data is output on a 12-bit digital video bus. This bus can be
tri-stated by asserting the
TriState
bit in the VIDEOMODE1 reg-
ister.
14.1
A programmable matrix switch is provided to map the output of
the internal pixel framer to the pins of the digital video bus as
illustrated in Figure 33.
Internal Pixel Framer Output Register
8
7
6
10
Digital Video Data Out Bus (d[11:0])
Figure 33. Digital Video Bus Switching Modes
This feature allows a programmable digital gain to be imple-
mented when connecting the sensor to 8 or 10 bit digital video
processing systems as illustrated in Figure 34. The unused bits
on the digital video bus can be optionally tri-stated.
Figure 34. Example of connection to 10/8 bit systems
Synchronisation Signals in Master Mode
By default the sensor’s digital video port’s synchronisation sig-
nals are configured to operate in master mode. In master mode
the integrated timing and control block controls the flow of data
onto the 12-bit digital port, three synchronisation outputs are
provided:
pclk
is the pixel clock output pin.
hsync
is the horizontal synchronisation output signal.
vsync
is the vertical synchronisation output signal.
14.2
The pixel clock output pin,
pclk,
is provided to act as a synchro-
nisation reference for the pixel data appearing at the digital
video out bus pins d[11:0]. This pin can be programmed to oper-
ate in two modes:
In free running mode the pixel clock output pin,
pclk,
is always
running with a fixed period. Pixel data appearing on the digital
video bus
d[11:0]
are synchronized to a specified active edge
of the clock as shown in Figure 35.
Pixel Clock Output Pin (pclk) (Master Mode)
Figure 35.
pclk
in Free Running Mode
In data ready mode, the pixel clock output pin (
pclk
) will pro-
duce a pulse with a specified level every time valid pixel data
appears on the digital video bus
d[11:0]
as shown in Figure
36.
d11
9
d10
d9
a) MSB Bit 11, Switch Mode (default)
d8
d7
5
d6
4
d5
3
d4
2
d3
1
d2
0
d1 d0
b) MSB Bit 10, Switch Mode
d) MSB bit 8, Switch Mode
Internal Pixel Framer Output Register
9
8
7
6
10
11
d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
5
4
3
2
1
0
c) MSB bit 9, Switch Mode
d0
Internal Pixel Framer Output Register
9
8
7
10
11
d11 d10 d9 d8 d7 d6 d5 d4 d3
d2
d1
6
5
4
3
2
1
0
Internal Pixel Framer Output Register
9
8
7
10
11
d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1
6
5
4
3
2
1
0
d0
10 bit
Digital
Image
Processor
d9
d8
d7
d6
d5
d4
d3
d2
d1
d0
d11
d10
d9
d8
d7
d6
d5
d4
d3
d2
d1
d0
LM9617
8 bit
Digital
Image
Processor
d7
d6
d5
d4
d3
d2
d1
d0
d11
d10
d9
d8
d7
d6
d5
d4
d3
d2
d1
d0
LM9617
a) LM9617 Connected to a 10 bit Digital Image Processors
b) LM9617 Connected to a 8 bit Digital Image Processors
pclk
d[11:0]
pclk
d[11:0]
a) pclk active edge negative
b) pclk active edge positive (default)
invalid pixel data
L
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