參數(shù)資料
型號(hào): LM87
廠商: National Semiconductor Corporation
英文描述: Serial Interface System Hardware Monitor with Remote Diode Temperature Sensing
中文描述: 串行接口系統(tǒng)硬件監(jiān)控與遠(yuǎn)程二極管溫度傳感器
文件頁(yè)數(shù): 27/32頁(yè)
文件大?。?/td> 470K
代理商: LM87
Functional Description
(Continued)
13.7 Interrupt Status Register 2—Address 42h
Power on default –
<
7:0
>
= 0000 0000 binary
Bit
0
1
2
3
4
5
6
7
Name
Read/Write
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Description
+12Vin
Vccp2
Reserved
Reserved
CI
THERM#
D1 Fault
D2 Fault
A one indicates a High or Low limit has been exceeded.
A one indicates a High or Low limit has been exceeded.
A one indicates the CI (Chassis Intrusion) input has gone high.
A one indicates the THERM# input has been pulled low by external circuitry.
A one indicates the D1 inputs are shorted to Vcc or open circuit.
A one indicates the D2 inputs are shorted to Vcc or open circuit.
13.8 Interrupt Mask Register 1—Address 43h
Power on default –
<
7:0
>
= 0000 0000 binary
Bit
0
1
2
3
4
5
6
7
Name
+2.5Vin/D2+
Vccp1
Vcc
+5Vin
Int. Temp.
Ext. Temp.
FAN1/AIN1
FAN2/AIN2
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Description
A one disables the corresponding interrupt status bit for INT
#
interrupt.
A one disables the corresponding interrupt status bit for INT
#
interrupt.
A one disables the corresponding interrupt status bit for INT
#
interrupt.
A one disables the corresponding interrupt status bit for INT
#
interrupt.
A one disables the corresponding interrupt status bit for INT
#
interrupt.
A one disables the corresponding interrupt status bit for INT
#
interrupt.
A one disables the corresponding interrupt status bit for INT
#
interrupt.
A one disables the corresponding interrupt status bit for INT
#
interrupt.
13.9 Interrupt Mask Register 2—Address 44h
Power on default –
<
7:0
>
= 0000 0000 binary
Bit
0
1
2
3
4
5
6
7
Name
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Description
+12Vin
Vccp2
Reserved
Reserved
Chassis Intrusion
THERM#
D1 Fault
D2 Fault
A one disables the corresponding interrupt status bit for INT
#
interrupt.
A one disables the corresponding interrupt status bit for INT
#
interrupt.
A one disables the corresponding interrupt status bit for INT
#
interrupt.
A one disables the corresponding interrupt status bit for INT
#
interrupt.
A one disables the corresponding interrupt status bit for INT
#
interrupt.
A one disables the corresponding interrupt status bit for INT
#
interrupt.
13.10 Reserved Register —Address 45h
Power on default –
<
7:0
>
= 00h. Read/Write for backwards
compatibility.
13.11 CI Clear Register—Address 46h
Power on default –
<
7:0
>
= 0000 0000 binary
Bit
0-6
7
Name
Read/Write
Read/Write
Read/Write
Description
Reserved
CI Clear
A one outputs a minimum 20 ms (minimum) active low pulse on the Chassis Intrusion
pin. The register bit self clears after the pulse has been output.
13.12 VID0-3/Fan Divisor Register—Address 47h
Power on default –
<
7:4
>
is 0101, and
<
3:0
>
is mapped to
VID
<
3:0
>
Bit
0-3
Name
Read/Write
Read Only
Description
VID
<
3:0
>
The VID
<
3:0
>
inputs from the Pentium/PRO power supplies that indicate the
operating voltage (e.g. 1.5 V to 2.9 V).
L
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27
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