參數(shù)資料
型號(hào): LM81CIMTX-3
英文描述: Single-Ended Data Acquisition System
中文描述: 單端數(shù)據(jù)采集系統(tǒng)
文件頁(yè)數(shù): 3/33頁(yè)
文件大小: 414K
代理商: LM81CIMTX-3
Block Diagram
Pin Description
Pin
Name(s)
Pin
Number
1
Number
of Pins
1
Type
Description
A0/NTEST_OUT
Digital I/0
The lowest order programmable bit of the serial bus address. This
pin functions as an output during NAND Tree tests (board-level
connectivity testing). Refer to SECTION 11 on NAND Tree testing.
The highest order programmable bit of the serial bus address.
Serial Bus bidirectional Data. Open-drain output.
Serial Bus Clock.
Schmitt Trigger fan tachometer inputs.
An active high input from an external circuit which latches a
Chassis Intrusion event. This line can go high without any
clamping action regardless of the powered state of the LM81.
There is also an internal open-drain output on this line, controlled
by Bit 6 of the Configuration Register (40h) or Bit 7 CI Clear
Register (46h), to provide a minimum 20 ms reset pulse. See
Section 3.3 and Section 9.0
Critical Temperature Alarm active low open-drain output. This pin
can be grounded when not used.
+3.3V V
+
power. Bypass with the parallel combination of 10 μF
(electrolytic or tantalum) and 0.1 μF (ceramic) bypass capacitors.
A1
SMBData
SMBCLK
FAN1-FAN2
CI
2
3
4
1
1
1
2
1
Digital Input
Digital I/O
Digital Input
Digital Inputs
Digital I/O
5-6
7
T_CRIT_A
8
1
Digital Output
V
+
(+2.8V to
+3.8V)
9
1
POWER
DS100072-2
L
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