參數(shù)資料
型號: LM80CIMT-3
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 電源管理
英文描述: Serial Interface ACPI-Compatible Microprocessor System Hardware Monitor
中文描述: 7-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO24
封裝: PLASTIC, TSSOP-24
文件頁數(shù): 23/29頁
文件大?。?/td> 435K
代理商: LM80CIMT-3
Functional Description
(Continued)
12.3 Configuration Register— Address 00h
Power on default
<
7:0
>
= 00001000 binary
Bit
Name
Read/
Write
Read/Write
Description
0
Start
A one enables startup of monitoring operations, a zero puts the part in standby mode.
Note:
The outputs of Interrupt pins will not be cleared if the user writes a zero to this
location after an interrupt has occurred unlike “INT_Clear” bit.At start up, limit checking
functions and scanning begin. Note, all limits should be set in the Value RAM before
setting this bit HIGH.
A one enables the INT Interrupt output.
A one selects an active high open source output while a zero selects an active low
open drain output.
A one disables the INT and RST_OUT/OS outputs without affecting the contents of
Interrupt Status Registers. The device will stop monitoring. It will resume upon clearing
of this bit.
A one outputs at least a 10 ms active low reset signal at RESET, if
<
7
>
= 1 and
<
6
>
= 0 in the Fan Divisor/RST_OUT/OS Register. This bit is cleared once the pulse
has gone inactive.
A one clears the CI (Chassis Intrusion) pin. This bit clears itself after the CI pins
cleared.
A one in this bit drives a one on GPO (General Purpose Output) pin.
A one restores power on default value to the Configuration Register, Interrupt Status
Registers, Interrupt Mask Registers, Fan Divisor/RST_OUT/OSRegister, and the OS
Configuration/Temperature Resolution Register. This bit clears itself since the power
on default is zero.
1
2
INT Enable
INT polarity
select
INT_Clear
Read/Write
Read/Write
3
Read/Write
4
RESET
Read/Write
5
Chassis Clear
Read/Write
6
7
GPO
INITIALIZATION
Read/Write
Read/Write
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