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參數(shù)資料
| 型號： | LM80CIMT-31 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Serial Interface ACPI-Compatible Microprocessor System Hardware Monitor |
| 中文描述： | 串行接口ACPI的兼容微處理器系統(tǒng)硬件監(jiān)視器 |
| 文件頁數(shù)： | 20/29頁 |
| 文件大小： | 435K |
| 代理商： | LM80CIMT-31 |
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Functional Description
(Continued)
INT_IN -
way to chain the INT (Interrupt) from other devices
through the LM80 to the processor.
This active low Interrupt merely provides a
8.2 INTERRUPT OUTPUTS
All Interrupts are indicated in the two Interrupt Status Regis-
ters.
INT
output has two mask registers, and individual masks for
each Interrupt. As described in Section 3.3, this hardware In-
terrupt line can also be enabled/disabled in the Configuration
Register. The Configuration Register is also used to set the
mode of the INT Interrupt line.
OS
is dedicated to the Temperature reading WATCHDOG. In
the “Fan Divisor/RST_OUT/OS Register” the OS enable bit
(Bit-6), must be set high and the RST enable bit (Bit -7) must
be set low to enable the OS function on the RST_OUT/OS
pin. OS pin has two modes of operation: “One-Time Inter-
rupt” and “Comparator”. “One-Time Interrupt” mode is se-
lected by taking bit-2 of the “OS Configuration/Temperature
Resolution Register” high. If bit-2 is taken low “Comparator”
mode is selected. Unlike the OS pin, the OS bit in “Interrupt
Status Register 2” functions in “Default Interrupt” and
“One-Time Interrupt” modes. The OS bit can be masked to
INT pin by taking bit-5 in the “Interrupt Mask Register 2” low.
A description of “Comparator”, “Default Interrupt” and
“One-Time Interrupt” modes can be found in Section 7.1.
8.3 INTERRUPT CLEARING
Reading an Interrupt Status Register will output the contents
of the Register, and reset the Register. A subsequent read
done before the analog “round-robin” monitoring loop is
complete will indicate a cleared Register. Allow at least 1.5
seconds to allow all Registers to be updated between reads.
In summary, the Interrupt Status Register clears upon being
read, and requires at least 1.5 seconds to be updated. When
the Interrupt Status Register clears, the hardwire interrupt
line will also clear until the Registers are updated by the
monitoring loop. The hardware Interrupt lines are cleared
with the INT_Clear bit, which is Bit 3 of the Configuration
Register, without affecting the contents of the Interrupt (INT)
Status Registers. When this bit is high, the LM80 monitoring
loop will stop. It will resume when the bit is low.
9.0 RST and GPO OUTPUTS
In PC applications the open drain GPO provides a gate drive
signal to an external P-channel MOSFET power switch. This
external MOSFET then would keep power turned on regard-
less of the state of front panel power switches when software
power control is used. In any given application this signal is
not limited to the function described by its label. For ex-
ample, since the LM80 incorporates temperature sensing,
the GPO output could also be utilized to control power to a
cooling fan. Take GPO active low by setting Bit 6 in the Con-
figuration Register low.
RST is intended to provide a master reset to devices con-
nected to this line. The RST_OUT/OS Control bit in Fan
Divisor/RST_OUT/OS Register, Bit 7, must be set high to en-
able this function. Setting Bit 4 in the Configuration Register
high outputs a least 10 ms low on this line, at the end of
which Bit 4 in the Configuration Register automatically
clears. Again, the label for this pin is only its suggested use.
In applications where the RST capability is not needed it can
be used for any type of digital control that requires a 10 ms
active low open drain output.
10.0 NAND TREE TESTS
A NAND tree is provided in the LM80 for Automated Test
Equipment (ATE) board level connectivity testing. If the user
applies a logic zero to the NTEST_IN/Reset_IN input pin, the
device will be in the NAND tree test mode. A0/NTEST_OUT
will become the NAND tree output pin. To perform a NAND
tree test all pins included in the NAND tree should be driven
to 1. Beginning with IN0 and working clockwise around the
chip, each pin can be toggled and a resulting toggle can be
observed on A0/NTEST_OUT. The following pins are ex-
cluded from the NAND tree test: GNDA (analog ground),
GND (digital ground), V + (power supply), A0/NTEST_OUT,
NTEST_IN/Reset_IN and RST_OUT/OS. Allow for a typical
propagation delay of 500 ns.
www.national.com
20
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