參數(shù)資料
型號(hào)： LM78
廠商： National Semiconductor Corporation
英文描述： Microprocessor System Hardware Monitor
中文描述： 微處理器系統(tǒng)硬件監(jiān)視器
文件頁(yè)數(shù)： 27/31頁(yè)
文件大小： 424K
代理商： LM78
Functional Description
(Continued)
13.7 SMI Mask Register 2—Address 44h
Power on default
<
7:0
>
= 00h
Bit
Name
Read/
Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Description
0
1
2
3
4
5
6
7
IN4
-IN5
-IN6
FAN3
Chassis Intrusion
FIFO Overflow
SMI__IN
RESET Enable
A one disables the corresponding interrupt status bit for SMI interrupt.
A one disables the corresponding interrupt status bit for SMI interrupt.
A one disables the corresponding interrupt status bit for SMI interrupt.
A one disables the corresponding interrupt status bit for SMI interrupt.
A one disables the corresponding interrupt status bit for SMI interrupt.
A one disables the corresponding interrupt status bit for SMI interrupt.
A one disables the corresponding interrupt status bit for SMI interrupt.
<
7
>
= 1 in SMI Mask Register 2 enables the RESET in the Configuration Register.
13.8 NMI Mask Register 1—Address 45h
Power on default
<
7:0
>
= 00h
Bit
Name
Read/
Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Description
0
1
2
3
4
5
6
7
IN0
IN1
IN2
IN3
Temperature
BTI
FAN1
FAN2
A one disables the corresponding interrupt status bit for NMI/IRQ interrupt.
A one disables the corresponding interrupt status bit for NMI/IRQ interrupt.
A one disables the corresponding interrupt status bit for NMI/IRQ interrupt.
A one disables the corresponding interrupt status bit for NMI/IRQ interrupt.
A one disables the corresponding interrupt status bit for NMI/IRQ interrupt.
A one disables the corresponding interrupt status bit for NMI/IRQ interrupt.
A one disables the corresponding interrupt status bit for NMI/IRQ interrupt.
A one disables the corresponding interrupt status bit for NMI/IRQ interrupt.
13.9 NMI Mask Register 2—Address 46h
Power on
<
7:0
>
= 01000000 binary
Bit
Name
Read/
Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Description
0
1
2
3
4
5
6
IN4
-IN5
-IN6
FAN3
Chassis Intrusion
FIFO Overflow
SMI__IN
A one disables the corresponding interrupt status bit for NMI/IRQ interrupt.
A one disables the corresponding interrupt status bit for NMI/IRQ interrupt.
A one disables the corresponding interrupt status bit for NMI/IRQ interrupt.
A one disables the corresponding interrupt status bit for NMI/IRQ interrupt.
A one disables the corresponding interrupt status bit for NMI/IRQ interrupt.
A one disables the corresponding interrupt status bit for NMI/IRQ interrupt.
A one disables the corresponding interrupt status bit for NMI/IRQ interrupt.
Note:
The Power on default is
1
for this bit.
A one outputs a minimum 20 ms active low pulse on the Chassis Intrusion pin. The
register bit self clears after the pulse has been output.
7
Chassis Clear
Read/Write
L
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