參數(shù)資料
型號(hào): LM5027AMHX
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 穩(wěn)壓器
英文描述: SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PDSO20
封裝: TSSOP-20
文件頁數(shù): 11/28頁
文件大小: 561K
代理商: LM5027AMHX
Gate Drive Outputs
The LM5027A contains three unique gate drivers. OUTA, the
primary switch driver, is designed to drive the gate of an N-
Channel MOSFET and is capable of sourcing and sinking a
peak current of 2A. The active clamp drive, OUTB, is de-
signed to drive a P-Channel MOSFET and is capable of
sourcing and sinking peak currents of 1A. The third driver,
OUTSR, is designed to drive the gate of a synchronous rec-
tification MOSFET through a gate drive transformer. OUTSR
gate driver has a source and sink capability of 3A.
Driver Delay Timing
The three independent time delay adjustments allow a great
deal of flexibility for the user to optimize the efficiency of the
system. The active clamp output (OUTB) is in phase with the
main output (OUTA), with the active clamp output overlapping
the main output. The overlap time provides dead-time be-
tween the operation of the main switch and the P-Channel
active clamp switch at both the rising and falling edges. The
rising edge control is set by a resistor from the TIME1 pin to
the AGND pin. The falling edge control is set with a resistor
from the TIME3 pin to the AGND pin.
The rising edge of the PWM comparator output coincides with
the rising edge of OUTB and the falling edge of the OUTSR
output without delay, as shown in Figure 9. The rising edge
control for turning on the OUTSR output after the main output
(OUTA) has turned off is set with a resistor from the TIME2
pin to the AGND pin. The PWM output goes high (see Figure
9) at the beginning of the oscillator cycle. The rising edge of
OUTA is delayed by time delay T1. The T1 delay directly af-
fects the maximum PWM duty cycle. The maximum duty cycle
is calculated using the following equation:
30111911
FIGURE 9. LM5027A Driver Output Timing
Thermal Protection
Internal Thermal Shutdown circuitry is provided to protect the
integrated circuit in the event the maximum rated junction
temperature is exceeded. When activated, typically at 165°C,
the controller is forced into a low power standby state with the
output drivers (OUTA, OUTB, and OUTSR), the bias regula-
tors (VCC and REF) disabled. The thermal protection feature
is provided to prevent catastrophic failures from accidental
device overheating. During a restart, after thermal shutdown,
the soft-start capacitors (SS and SSSR) are fully discharged
and the controller follows a normal start-up sequence after the
junction temperature falls below the Thermal Shutdown hys-
teresis threshold (typically 145°C).
VIN
The voltage applied to the VIN pin, normally the same as the
system voltage applied to the power transformer’s primary
(V
PWR), can vary in the range of the 13 to 90V with transient
capability of 105V. The current into VIN depends primarily on
the output driver capacitive loads, the switching frequency,
and any external loads on the VCC pin. If the power dissipa-
tion associated with the VIN current exceeds the package
capability, an external voltage should be applied to the VCC
pin (see Figure 10) to disable the internal start-up regulator.
The VCC regulation set point voltage is initially internally reg-
ulated to 9.5V. After the first OUTSR pulse, the VCC set point
voltage is reduced to 7.5V. If an external voltage is applied to
the VCC pin the required range is 8V to 15V . The VIN to VCC
series pass regulator includes a parasitic diode between VIN
and VCC. This diode should not be forward biased in normal
operation. The VCC voltage should never exceed the VIN
voltage. It is recommended the circuit of Figure 10 be used to
suppress transients which may occur at the input supply, in
particular where VIN is operated close to the maximum op-
erating rating of the LM5027A.
30111912
FIGURE 10. Start-up Regulator Power Reduction
19
www.national.com
LM5027A
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