
Pin Descriptions
Pin
Name
Description
Application Information
1
VIN
Input voltage source
Input to the Start-up Regulator. Operating input range is 13V to 90V.
The Absolute Maximum Rating is 105V. For power sources outside of
this range, the LM5027A can be biased directly at VCC by an external
regulator.
2
RAMP
Feed-forward modulation ramp
An external RC circuit from VIN sets the PWM ramp slope. This pin is
discharged at the conclusion of every cycle by an internal FET. An
internal comparator terminates the PWM pulse if the RAMP pin
exceeds 2.5V thus limiting the maximum volt-second product to the
transformer primary.
3
TIME3
Overlap delay 3
An external resistor sets the overlap delay for the active clamp output.
The R
TIME3 resistor connected between TIME3 and AGND sets the
OUTA turn-off (falling edge) to OUTB turn-on (falling edge) pulse delay.
See Fig. 9.
4
TIME2
Overlap delay 2
An external resistor sets the overlap delay for the OUTSR output. The
R
TIME2 resistor connected between TIME2 and AGND sets the OUTA
turn-off (falling edge) to OUTSR turn-on (rising edge) pulse delay. See
Fig. 9.
5
TIME1
Overlap delay 1
An external resistor sets the overlap delay for the active clamp output.
The R
TIME1 resistor connected between TIME1 and AGND sets the
OUTB and OUTSR turn-off to OUTA turn-on pulse delay. See Fig. 9.
6
AGND
Analog ground
Connect directly to Power Ground.
7
RT
Oscillator frequency control and sync
clock input
Normally biased at 2V by an internal amplifier. An external resistor
connected between RT and AGND sets the internal oscillator
frequency. The internal oscillator can be synchronized to an external
clock with a frequency higher than the free running frequency set by
the RT resistor.
8
COMP
Input to the pulse width modulator
An external opto-coupler connected to the COMP pin sources current
into an internal NPN current mirror. The PWM duty cycle is at its
maximum value with zero input current, while 1mA reduces the duty
cycle to zero. The current mirror improves the frequency response by
reducing the ac voltage across the opto-coupler detector transistor.
9
REF
Reference Output
Output of a 5V reference. Maximum output current is 10 mA. Locally
decouple with a 0.1 F capacitor.
10
OUTB
Output driver
Control output of the active clamp PFET gate. Capable of 1A peak
source and sink current.
11
OUTA
Output driver
Control output of the main PWM NFET gate. Capable of 2A peak
source and sink current.
12
OUTSR
Output driver
Control output of the secondary side synchronous rectifier FET gates.
Capable of 3A peak source and sink current.
13
PGND
Power ground
Connect directly to Analog Ground
14
VCC
Start-up regulator output
Output of the internal high voltage start-up regulator. Regulated at 9.5V
during start-up and 7.5V during run mode. If the auxiliary winding raises
the voltage on this pin above the regulation set point, the internal start-
up regulator will shutdown, thus reducing the IC power dissipation.
15
CS
Current sense input
Current sense input for cycle-by-cycle current limiting. If the CS pin
exceeds 500mV the output pulse will be terminated, entering cycle-by-
cycle current limit. An internal switch holds CS low for 100 ns after
OUTA switches high to blank leading edge transients.
16
SS
Soft-start Input
An internal 22 A current source charges an external capacitor to set
the soft-start rate.
3
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LM5027A