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參數(shù)資料
| 型號(hào)： | LM4921 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Low Voltage I2S 16-Bit Stereo DAC with Stereo Headphone Power Amplifiers and Volume Control |
| 中文描述： | 低電壓的I2S 16位立體聲DAC立體聲耳機(jī)功率放大器和音量控制 |
| 文件頁(yè)數(shù)： | 13/18頁(yè) |
| 文件大?。?/td> | 849K |
| 代理商： | LM4921 |
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Application Information
(Continued)
SPI TIMING DIAGRAM
200486G1
SPI OPERATIONAL REQUIREMENTS
1. The maximum clock rate is 5MHz for the CLK pin.
2. CLK must remain logic-high for at least 100ns (t
) after
the rising edge of CLK, and CLK must remain logic-low for at
least 100ns (t
CL
) after the falling edge of CLK.
3. Data bits are written to the DATA pin with the least
significant bit (LSB) first.
4. The serial data bits are sampled at the rising edge of CLK.
Any transition on DATA must occur at least 20ns (t
) before
the rising edge of CLK. Also, any transition on DATA must
occur at least 20ns (t
) after the rising edge of CLK and
stabilize before the next rising edge of CLK.
5. ENABLE should be logic-high only during serial data
transmission.
6. ENABLE must be logic-high at least 20ns (t
) before the
first rising edge of CLK, and ENABLE has to remain logic-
high at least 20ns (t
EH
) after the sixteenth rising edge of
CLK.
7. If ENABLE remains logic-low for more than 10ns before all
16 bits are transmitted then the data latch will be aborted.
8. If ENABLE is logic-high for more than 16 CLK pulses then
only the first 16 data bits will be latched and activated at
rising edge of sixteenth CLK.
9. ENABLE must remain logic-low for at least 30ns (t
EL
).
10. Coincidental rising or falling edges of CLK and ENABLE
are not allowed. If CLK is to be held logic-high after the data
transmission, the falling edge of CLK must occur at least
20ns (t
) before ENABLE transitions to logic-high for the
next set of data.
I2S INTERFACE BUS (J2 - Fig 2)
The I2S standard provides a uni-directional serial interface
designed specifically for digital audio. For the LM4921, the
interface provides access to a 48kHz, 16 bit full-range stereo
audio DAC. This interface uses a three wire system of clock
(I2S_CLK), data (I2S_DATA), and word select (I2S_WS,
sometimes called Right/Left Select).
Abit clock (I2S_CLK) at 32 or 64 times the sample frequency
is established by the I2S system master and the word select
(I2S_WS) line is driven at a frequency equal to the sampling
rate of the audio data, in this case 48kHz. The word line is
registered to change on the positive edge of the bit clock.
The serial data (I2S_DATA) is sent MSB first, again registers
on the positive edge of the bit clock, delayed by 1 bit clock
cycle relative to the changing of the word line (typical I
2
S
format).
MCLK/XTAL_IN (S1 MCLK SEL - Fig 2)
This is the input for an external Master Clock. The jumper at
S1 must be removed (disconnecting the onboard crystal
from the circuit) when using an external Master Clock.
STEREO HEADPHONE OUTPUT JACK (J3 - Fig 2)
This is the stereo headphone output. Each channel is single-
ended, with 100uF DC output blocking capacitors mounted
on the demo board (C6 and C7). These capacitors are
necessary to block the 1/2 VDD DC bias and prevent it from
flowing through the headphone speakers (DC current will
destroy most audio speakers) while allowing the audio ac
signal to pass through. The jack features a typical stereo
headphone pinout.
L
www.national.com
13
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LM4921ITL | 制造商:Texas Instruments 功能描述:16BIT STEREO DAC + AMP SMD 4921 |
| LM4921ITL/NOPB | 功能描述:音頻放大器 RoHS:否 制造商:STMicroelectronics 產(chǎn)品:General Purpose Audio Amplifiers 輸出類型:Digital 輸出功率: THD + 噪聲: 工作電源電壓:3.3 V 電源電流: 最大功率耗散: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-64 封裝:Reel |
| LM4921ITLEVAL | 功能描述:音頻 IC 開(kāi)發(fā)工具 LM4921ITL EVAL BOARD RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評(píng)估:TAS5614L 工作電源電壓:12 V to 38 V |
| LM4921ITLX | 制造商:Texas Instruments 功能描述:IC,Audio Amplifier,DUAL,BGA,20PIN,PLASTIC |
| LM4921ITLX/NOPB | 功能描述:音頻放大器 RoHS:否 制造商:STMicroelectronics 產(chǎn)品:General Purpose Audio Amplifiers 輸出類型:Digital 輸出功率: THD + 噪聲: 工作電源電壓:3.3 V 電源電流: 最大功率耗散: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-64 封裝:Reel |
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