- 您現在的位置：買賣IC網 > PDF目錄10367 > LM4855LQ/NOPB (National Semiconductor)IC AMP AUDIO PWR 1.5W MONO 24LLP PDF資料下載
參數資料
| 型號： | LM4855LQ/NOPB |
| 廠商： | National Semiconductor |
| 文件頁數： | 8/27頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC AMP AUDIO PWR 1.5W MONO 24LLP |
| 標準包裝： | 1 |
| 系列： | Boomer® |
| 類型： | AB 類 |
| 輸出類型： | 1-通道（單聲道），帶立體聲耳機 |
| 在某負載時最大輸出功率 x 通道數量： | 1.5W x 1 @ 4 歐姆; 115mW x 2 @ 32 歐姆 |
| 電源電壓： | 2.6 V ~ 5 V |
| 特點： | 消除爆音，靜音，關機，SPI，熱保護，音量控制 |
| 安裝類型： | 表面貼裝 |
| 供應商設備封裝： | 24-LLP-EP（4x5） |
| 封裝/外殼： | 24-WFQFN 裸露焊盤 |
| 包裝： | 標準包裝 |
| 配用： | LM4855LQBD-ND - BOARD EVALUATION LM4855LQ |
| 其它名稱： | LM4855LQDKR |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁當前第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁
SNAS164C – JUNE 2002 – REVISED MAY 2013
SPI OPERATIONAL REQUIREMENTS
1. The data bits are transmitted with the LSB first.
2. The maximum clock rate is 10MHz for the CLK pin.
3. CLK must remain logic-high for at least 50ns (tCH ) after the rising edge of CLK, and CLK must remain logic-
low for at least 50ns (tCL) after the falling edge of CLK.
4. The serial data bits are sampled at the rising edge of CLK. Any transition on DATA must occur at least 20ns
(tDS) before the rising edge of CLK. Also, any transition on DATA must occur at least 20ns (tDH) after the rising
edge of CLK and stabilize before the next rising edge of CLK.
5. ENB should be logic-high only during serial data transmission.
6. ENB must be logic-high at least 20ns (tES ) before the first rising edge of CLK, and ENB has to remain logic-
high at least 20ns (tEH) after the eighth rising edge of CLK.
7. If ENB remains logic-low for more than 10ns before all 8 bits are transmitted then the data latch will be
aborted.
8. If ENB is logic-high for more than 8 CLK pulses then only the first 8 data bits will be latched and activated
when ENB transitions to logic-low.
9. ENB must remain logic-low for at least 30ns (tEL ) to latch in the data.
10. Coincidental rising or falling edges of CLK and ENB are not allowed. If CLK is to be held logic-high after the
data transmission, the falling edge of CLK must occur at least 20ns (tCS) before ENB transitions to logic-high for
the next set of data.
Figure 37. SPI Timing Diagram
16
Copyright 2002–2013, Texas Instruments Incorporated
Product Folder Links: LM4855
相關PDF資料 |
PDF描述 |
|---|---|
| MS27472T10C99P | CONN RCPT 7POS WALL MT W/PINS |
| MS27497T10F98PB | CONN RCPT 6POS WALL MNT W/PINS |
| MS27497T10F98PD | CONN RCPT 6POS WALL MNT W/PINS |
| VE-2NH-MX-S | CONVERTER MOD DC/DC 52V 75W |
| MS3106A24-7S | CONN PLUG 16POS STRAIGHT W/SCKT |
相關代理商/技術參數 |
參數描述 |
|---|---|
| LM4855LQX/NOPB | 制造商:Texas Instruments 功能描述:Audio Amp Headphone/Speaker 1-CH Mono/2-CH Stereo 1.5W Class-AB 24-Pin LLP EP T/R |
| LM4856 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Integrated Audio Amplifier System |
| LM48560 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:High Voltage Class H Ceramic Speaker Driver with Automatic Level Control |
| LM48560TL | 制造商:TI 制造商全稱:Texas Instruments 功能描述:High Voltage Class H Ceramic Speaker Driver with Automatic Level Control |
| LM48560TL/NOPB | 功能描述:音頻放大器 Hi Vltg Class H Cer Speaker Driver RoHS:否 制造商:STMicroelectronics 產品:General Purpose Audio Amplifiers 輸出類型:Digital 輸出功率: THD + 噪聲: 工作電源電壓:3.3 V 電源電流: 最大功率耗散: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:TQFP-64 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復。