參數資料
型號: LM4851
廠商: National Semiconductor Corporation
元件分類: 運動控制電子
英文描述: Integrated Audio Amplifier System
中文描述: 集成音頻放大器系統(tǒng)
文件頁數: 13/22頁
文件大?。?/td> 1126K
代理商: LM4851
Application Information
SPI PIN DESCRIPTION
DATA: This is the serial data input pin.
CLK: This is the clock input pin.
ENB: This is the SPI enable pin and is active-high.
SPI OPERATION DESCRIPTION
The serial data bits are organized into a field which contains
8 bits of data defined by TABLE 1. The Data 0 to Data 2 bits
determine the output mode of the LM4851 as shown in
TABLE 2. The Data 3 to Data 7 bits determine the volume
level setting as illustrated by TABLE 3. For each SPI transfer,
the data bits are written to the DATA pin with the least
significant bit (LSB) first. All serial data are sampled at the
rising edge of the CLK signal. Once all the data bits have
been sampled, ENB transitions from logic-high to logic-low
to complete the SPI sequence. All 8 bits must be received
before any data latch can occur. Any excess CLK and DATA
transitions will be ignored after the eighth rising clock edge
has occurred. For any data sequence longer than 8 bits, only
the first 8 bits will get loaded into the shift register and the
rest of the bits will be disregarded.
TABLE 1. Bit Allocation
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Mode 1
Mode 2
Mode 3
Volume 1
Volume 2
Volume 3
Volume 4
Volume 5
TABLE 2. Output Mode Selection
Output Mode #
0
1
2
3
4
5
6
7
P = Phone In
R = Rin
L = Lin
SD = Shutdown
G = Gain of volume control
Default Mode upon device power-up is Output Mode 0
Data 2
0
0
0
0
1
1
1
1
Data 1
0
0
1
1
0
0
1
1
Data 0
0
1
0
1
0
1
0
1
SPKR
OUT
SD
6dB x P
SD
G(R+L)
SD
G(R+L) + 6dB x P
SD
6dB x P
R
OUT
SD
SD
P
SD
G x R
SD
(G x R) + P
(G x R) + P
L
OUT
SD
SD
P
SD
G x L
SD
(G x L) + P
(G x L) + P
L
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PDF描述
LM4851LQ Integrated Audio Amplifier System
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