參數(shù)資料
型號(hào): LM4845
廠商: National Semiconductor Corporation
英文描述: Output Capacitor-less Audio Subsystem with Programmable National 3D
中文描述: 輸出電容器的音頻子系統(tǒng),具有可編程全國三維
文件頁數(shù): 20/29頁
文件大?。?/td> 1392K
代理商: LM4845
Application Information
I
2
C PIN DESCRIPTION
SDA: This is the serial data input pin.
SCL: This is the clock input pin.
ID_ENB: This is the address select input pin.
I
2
CSPI_SEL: This is tied LOW for I
2
C mode.
I
2
C COMPATIBLE INTERFACE
The LM4845 uses a serial bus which conforms to the I
2
C
protocol to control the chip’s functions with two wires: clock
(SCL) and data (SDA). The clock line is uni-directional. The
data line is bi-directional (open-collector). The maximum
clock frequency specified by the I
2
C standard is 400kHz. In
this discussion, the master is the controlling microcontroller
and the slave is the LM4845.
The I
2
C address for the LM4845 is determined using the
ID_ENB pin. The LM4845’s two possible I
2
C chip addresses
are of the form 111110X
0 (binary), where X
= 0, if ID_ENB
is logic LOW; and X
= 1, if ID_ENB is logic HIGH. If the I
2
C
interface is used to address a number of chips in a system,
the LM4845’s chip address can be changed to avoid any
possible address conflicts.
The bus format for the I
2
C interface is shown in Figure 3. The
bus format diagram is broken up into six major sections:
The "start" signal is generated by lowering the data signal
while the clock signal is HIGH. The start signal will alert all
devices attached to the I
2
C bus to check the incoming ad-
dress against their own address.
The 8-bit chip address is sent next, most significant bit first.
The data is latched in on the rising edge of the clock. Each
address bit must be stable while the clock level is HIGH.
For I
2
C interface operation, the I
2
CSPI_SEL pin needs to be
tied LOW (and tied high for SPI operation).
After the last bit of the address bit is sent, the master
releases the data line HIGH (through a pull-up resistor).
Then the master sends an acknowledge clock pulse. If the
LM4845 has received the address correctly, then it holds the
data line LOW during the clock pulse. If the data line is not
held LOW during the acknowledge clock pulse, then the
master should abort the rest of the data transfer to the
LM4845.
The 8 bits of data are sent next, most significant bit first.
Each data bit should be valid while the clock level is stable
HIGH.
After the data byte is sent, the master must check for another
acknowledge to see if the LM4845 received the data.
If the master has more data bytes to send to the LM4845,
then the master can repeat the previous two steps until all
data bytes have been sent.
The "stop" signal ends the transfer. To signal "stop", the data
signal goes HIGH while the clock signal is HIGH. The data
line should be held HIGH when not in use.
I
2
C INTERFACE POWER SUPPLY PIN (I
2
CV
DD
)
The LM4845’s I
2
C interface is powered up through the
I
2
CV
pin. The LM4845’s I
2
C interface operates at a volt-
age level set by the I
2
CV
pin which can be set indepen-
dent to that of the main power supply pin V
. This is ideal
whenever logic levels for the I
2
C interface are dictated by a
microcontroller or microprocessor that is operating at a lower
supply voltage than the main battery of a portable system.
201059F5
FIGURE 3. I
2
C Bus Format
L
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