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參數(shù)資料
| 型號： | LM4844 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Stereo 1.2W Audio Sub-system with 3D Enhancement |
| 中文描述： | 1.2W的立體聲音頻子系統(tǒng)三維增強系統(tǒng) |
| 文件頁數(shù)： | 15/21頁 |
| 文件大?。?/td> | 983K |
| 代理商： | LM4844 |
Application Information
(Continued)
I
2
C COMPATIBLE INTERFACE
The LM4844 uses a serial bus, which conforms to the I
2
C
protocol, to control the chip’s functions with two wires: clock
(SCL) and data (SDA). The clock line is uni-directional. The
data line is bi-directional (open-collector). The maximum
clock frequency specified by the I
2
C standard is 400kHz. In
this discussion, the master is the controlling microcontroller
and the slave is the LM4844.
The I
2
C address for the LM4844 is determined using the
ADR pin. The LM4844’s two possible I
2
C chip addresses are
of the form 111110X
0 (binary), where X
= 0, if ADR is logic
low; and X
= 1, if ADR is logic high. If the I
2
C interface is
used to address a number of chips in a system, the
LM4844’s chip address can be changed to avoid any pos-
sible address conflicts.
The bus format for the I
2
C interface is shown in Figure 2. The
bus format diagram is broken up into six major sections:
The "start" signal is generated by lowering the data signal
while the clock signal is high. The start signal will alert all
devices attached to the I
2
C bus to check the incoming ad-
dress against their own address.
The 8-bit chip address is sent next, most significant bit first.
The data is latched in on the rising edge of the clock. Each
address bit must be stable while the clock level is high.
After the last bit of the address bit is sent, the master
releases the data line high (through a pull-up resistor). Then
the master sends an acknowledge clock pulse. If the
LM4844 has received the address correctly, then it holds the
data line low during the clock pulse. If the data line is not
held low during the acknowledge clock pulse, then the mas-
ter should abort the rest of the data transfer to the LM4844.
The 8 bits of data are sent next, most significant bit first.
Each data bit should be valid while the clock level is stable
high.
After the data byte is sent, the master must check for another
acknowledge to see if the LM4844 received the data.
If the master has more data bytes to send to the LM4844,
then the master can repeat the previous two steps until all
data bytes have been sent.
The "stop" signal ends the transfer. To signal "stop", the data
signal goes high while the clock signal is high. The data line
should be held high when not in use.
I
2
C INTERFACE POWER SUPPLY PIN (I
2
CV
DD
)
The LM4844’s I
2
C interface is powered up through the
I
2
CV
pin. The LM4844’s I
2
C interface operates at a volt-
age level set by the I
2
CV
pin which can be set indepen-
dent to that of the main power supply pin V
DD
. This is ideal
whenever logic levels for the I
2
C interface are dictated by a
microcontroller or microprocessor that is operating at a lower
supply voltage than the main battery of a portable system.
NATIONAL 3D ENHANCEMENT
The LM4844 features a 3D audio enhancement effect that
widens the perceived soundstage from a stereo audio signal.
The 3D audio enhancement improves the apparent stereo
channel separation whenever the left and right speakers are
too close to one another, due to system size constraints or
equipment limitations.
An external RC network, shown in Figure 1, is required to
enable the 3D effect. There are separate RC networks for
both the stereo loudspeaker outputs as well as the stereo
headphone outputs, so the 3D effect can be set indepen-
dently for each set of stereo outputs.
The amount of the 3D effect is set by the R
resistor.
Decreasing the value of R
will increase the 3D effect. The
C
capacitor sets the low cutoff frequency of the 3D effect.
Increasing the value of C
3D
will decrease the low cutoff
frequency at which the 3D effect starts to occur, as shown by
Equation 1.
f
3D(-3dB)
= 1 / 2
π
(R
3D
)(C
3D
)
(1)
Activating the 3D effect will cause an increase in gain by a
multiplication factor of (1 + 20k
/R
3D
). Setting R
3D
to 20k
will result in a gain increase by a multiplication factor of
(1+20k
/20k
) = 2 or 6dB whenever the 3D effect is acti-
vated. The volume control can be programmed through the
I
2
C compatible interface to compensate for the extra 6dB
increase in gain. For example, if the stereo volume control is
set at 0dB (11011 from Table 4) before the 3D effect is
activated, the volume control should be programmed to
–6dB (10111 from Table 4) immediately after the 3D effect
has been activated. Setting R
= 20k
and C
= 0.22μF
allows the LM4844 to produce a pronounced 3D effect with a
minimal increase in output noise.
OUTPUT CAPACITOR-LESS (OCL) OPERATION AND
LAYOUT TECHNIQUES FOR OPTIMUM CROSSTALK
The LM4844’s OCL headphone architecture eliminates out-
put coupling capacitors. Unless the headphone is in shut-
down, the OCL output will be at a bias voltage of
1
2
V
,
which is applied to the stereo headphone jack’s sleeve. This
voltage matches the bias voltage present on LHP and RHP
outputs that drive the headphones. The headphones operate
in a manner similar to a bridge-tied load (BTL). Because the
same DC voltage is applied to both headphone speaker
terminals there is no net DC current flow through the
speaker. AC current flows through a headphone speaker as
an audio signal’s output amplitude increases on the speak-
er’s terminal.
The headphone jack’s sleeve is not connected to circuit
ground when used in OCL mode. Using the headphone
output jack as a line-level output will place the LM4844’s
1
2
V
DD
bias voltage on a plug’s sleeve connection.
Since the LHP and RHP outputs of the LM4844 share the
OCL output as a reference, certain layout techniques should
be used in order to achieve optimum crosstalk performance.
The crosstalk will depend on the parasitic resistance of the
trace connecting the LM4844 OCL output to the headphone
jack sleeve and on the load resistance value. Since the load
resistance is often predetermined, it is advisable to use a
trace that is as short and as wide as possible. Reasonable
application of this layout technique will result in crosstalk
values of 60dB, as specified in the electrical characteristics
table.
BRIDGE CONFIGURATION EXPLANATION
The LM4844 consists of two sets of bridged-tied amplifier
pairs that drive the left loudspeaker (LLS) and the right
loudspeaker (RLS). For this discussion, only the LLS bridge-
tied amplifier pair will be referred to. The LM4844 drives a
load, such as a speaker, connected between outputs, LLS+
and LLS-. In the LLS amplifier block, the output of the
amplifier that drives LLS- serves as the input to the unity gain
inverting amplifier that drives LLS+.
L
www.national.com
15
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相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LM4844_07 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Stereo 1.2W Audio Sub-System with 3D Enhancement |
| LM4844TL/NOPB | 功能描述:接口—CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| LM4844TLEVAL | 功能描述:BOARD EVALUATION LM4844TL RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 音頻放大器 系列:Boomer® 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- |
| LM4844TLX/NOPB | 功能描述:接口—CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| LM4845 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Output Capacitor-less Audio Subsystem with Programmable National 3D |
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