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參數(shù)資料
| 型號(hào)： | LM4550VH/NOPB |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | 7 X 7 X 1.40 MM, LQFP-48 |
| 文件頁(yè)數(shù)： | 25/30頁(yè) |
| 文件大?。?/td> | 611K |
| 代理商： | LM4550VH/NOPB |
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Electrical Characteristics (Notes 1, 5) The following specifications apply for AV
DD = 5V, DVDD = 5V, Fs = 48
kHz, single codec configuration, unless otherwise noted. Limits apply for T
A= 25C. The reference for 0 dB is 1 Vrms unless
otherwise specified. (Continued)
Symbol
Parameter
Conditions
LM4550
Units
(Limits)
Typical
Limit
Analog to Digital Converters
Resolution
18
Bits
Dynamic Range (Note 9)
-60 dB Input THD+N, A-Weighted
90
86
dB (min)
Frequency Response
-1 dB Bandwidth
20
kHz
Digital to Analog Converters
Resolution
18
Bits
Dynamic Range (Note 9)
-60 dB Input THD+N, A-Weighted
89
85
dB (min)
THD
Total Harmonic Distortion
V
IN =-3dB,f=1 kHz, RL =10k
0.01
%
Frequency Response
20 - 21 k
Hz
Group Delay (Note 9)
2
ms (max)
Out of Band Energy (Note 10)
-40
dB
Stop Band Rejection
70
dB
D
T
Discrete Tones
-96
dB
Analog Output Section
A
S
Step Size
0 dB to -46.5 dB
1.5
dB
A
M
Mute Attenuation
86
dB
THD+N
Headphone Amplifier Total
Harmonic Distortion plus Noise
Loopthrough Mode (Note 8), R
L =32
,
f = 1 kHz, P
out =50mW
0.02
%
Z
OUT
Output Impedance (Note 9)
HP_OUT_L, HP_OUT_R
TBD
Z
OUT
Output Impedance (Note 9)
LINE_OUT_L, LINE_OUT_R,
MONO_OUT
TBD
Digital I/O (Note 9)
V
IH
High level input voltage
0.40 x
DV
DD
V (min)
V
IL
Low level input voltage
0.30 x
DV
DD
V (max)
V
OH
High level output voltage
0.50 x
DV
DD
V (min)
V
OL
Low level output voltage
0.20 x
DV
DD
V (max)
I
L
Input Leakage Current
AC Link inputs
±10
A
I
L
Tri state Leakage Current
High impedance AC Link outputs
±10
A
I
DR
Output drive current
AC Link outputs
5
mA
Digital Timing Specifications (Note 9)
F
BC
BIT_CLK frequency
12.288
MHz
T
BCP
BIT_CLK period
81.4
ns
T
CH
BIT_CLK high
Variation of BIT_CLK duty cycle from
50%
±20
% (max)
F
SYNC
SYNC frequency
48
kHz
T
SP
SYNC period
20.8
s
T
SH
SYNC high pulse width
1.3
s
T
SL
SYNC low pulse width
19.5
s
T
DSETUP
Setup Time for codec data input
SDATA_OUT to falling edge of BIT_CLK
15
ns (min)
T
DHOLD
Hold Time for codec data input
Hold time of SDATA_OUT from falling
edge of BIT_CLK
5
ns (min)
LM4550
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