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| 型號(hào)： | LM4120AI-4.1 |
| 廠商： | National Semiconductor Corporation |
| 元件分類： | 串行ADC |
| 英文描述： | Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold |
| 中文描述： | 自校準(zhǔn)12位帶符號(hào)串行I /辦公自動(dòng)化/ D轉(zhuǎn)換器MUX和采樣/保持 |
| 文件頁(yè)數(shù)： | 27/41頁(yè) |
| 文件大?。?/td> | 1152K |
| 代理商： | LM4120AI-4.1 |
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TABLE 5. Mode Programming
(Continued)
DI4
DI5
DI6
DI7
DI3
DI4
DI5
DI6
ADC12038
ADC12034
ADC12030
and
ADC12032
DI0
DI0
DI1
DI1
DI2
DI2
DI3
Mode Selected
(Current)
DO Format
(next Conversion
Cycle)
DI0
DI1
DI2
DI3
DI4
DI5
H
L
H
H
L
X
L
L
X
L
L
X
H
H
H
H
H
H
H
H
H
L
H
H
Acquisition Time—34 CCLK Cycles
User Mode
Test Mode
(CH1–CH7 become Active Outputs)
No Change
No Change
No Change
Note:
The A/D powers up with no Auto Cal, no Auto Zero, 10 CCLK acquisition time, 12-bit + sign conversion, power up, 12- or 13-bit MSB first, and user mode.
X = Don’t Care
TABLE 6. Conversion/Read Data Only Mode Programming
CS
L
L
H
X
CONV
L
H
X
X
PD
L
L
L
H
Mode
See
Table 5
for Mode
Read Only (Previous DO Format). No Conversion.
Idle
Power Down
X = Don’t Care
TABLE 7. Status Register
Status Bit
Location
Status Bit
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
PU
PD
Cal
8 or 9
12 or 13
16 or 17
DO Output Format Status
“High”
indicates a
16 or 17
bit format
sign bit is
included.
When
“Low” the
sign bit is
not
included.
Sign
Justification
Test Mode
Device Status
“High”
indicates a
Power
Down
Sequence
is in
progress
Function
“High”
indicates a
Power Up
Sequence
is in
progress
“High”
indicates
an
Auto-Cal
Sequence
is in
progress
“High”
indicates
an 8 or 9
bit format
“High”
indicates a
12 or 13
bit format
“High”
indicates
that the
When “High”
the
conversion
result will be
output MSB
first. When
“Low” the
result will be
output LSB
first.
When “High”
the device is
in test mode.
When “Low”
the device is
in user
mode.
Application Hints
1.0 DIGITAL INTERFACE
1.1 Interface Concepts
The example in
Figure 7
shows a typical sequence of events
after the power is applied to the ADC12030/2/4/8:
The first instruction input to the A/D via DI initiates Auto Cal.
The data output on DO at that time is meaningless and is
completely random. To determine whether the Auto Cal has
been completed, a read status instruction is issued to the
A/D. Again the data output at that time has no significance
since the Auto Cal procedure modifies the data in the output
shift register. To retrieve the status information, an additional
read status instruction is issued to the A/D. At this time the
status data is available on DO. If the Cal signal in the status
word, is low Auto Cal has been completed. Therefore, the
next instruction issued can start a conversion. The data
output at this time is again status information. To keep noise
from corrupting the A/D conversion, status can not be read
during a conversion. If CS is strobed and is brought low
during a conversion, that conversion is prematurely ended.
EOC can be used to determine the end of a conversion or
theA/D controller can keep track in software of when it would
be appropriate to comnmunicate to the A/D again. Once it
has been determined that the A/D has completed a conver-
sion, another instruction can be transmitted to the A/D. The
data from this conversion can be accessed when the next
instruction is issued to the A/D.
Note, when CS is low continuously it is important to transmit
the exact number of SCLK cycles, as shown in the timing
diagrams. Not doing so will desynchronize the serial com-
munication to the A/D. (See Section 1.3.)
01135436
FIGURE 7. Typical Power Supply Power Up Sequence
A
www.national.com
27
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