參數(shù)資料
型號(hào)： LM4030AI-4.1
廠商： National Semiconductor Corporation
元件分類： 串行ADC
英文描述： Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold
中文描述： 自校準(zhǔn)12位帶符號(hào)串行I /辦公自動(dòng)化/ D轉(zhuǎn)換器MUX和采樣/保持
文件頁(yè)數(shù)： 28/41頁(yè)
文件大?。?/td> 1152K
代理商： LM4030AI-4.1
Application Hints
(Continued)
1.2 Changing Configuration
The configuration of the ADC12030/2/4/8 on power up de-
faults to 12-bit plus sign resolution, 12- or 13-bit MSB First,
10 CCLK acquisition time, user mode, no Auto Cal, no Auto
Zero, and power up mode. Changing the aquisition time and
turning the sign bit on and off requires an 8-bit instruction to
be issued to the ADC. This instruction will not start a con-
version. The instructions that select a multiplexer address
and format the output data do start a conversion.
Figure 8
describes an example of changing the configuration of the
ADC12030/2/4/8.
During I/O sequence 1, the instruction on DI configures the
ADC12030/2/4/8 to do a conversion with 12-bit +sign reso-
lution. Notice that when the 6 CCLK Acquisition and Data
Out without Sign instructions are issued to the ADC, I/O
sequences 2 and 3, a new conversion is not started. The
data output during these instructions is from conversion N
which was started during I/O sequence 1. The Configuration
Modification timing diagram describes in detail the sequence
of events necessary for a Data Out without Sign, Data Out
with Sign, or 6/10/18/34 CCLK Acquisition time mode selec-
tion.
Table 5
describes the actual data necessary to be input
to theADC to accomplish this configuration modification. The
next instruction, shown in
Figure 8
, issued to the A/D starts
conversion N+1 with 8 bits of resolution formatted MSB first.
Again the data output during this I/O cycle is the data from
conversion N.
The number of SCLKs applied to the A/D during any conver-
sion I/O sequence should vary in accord with the data out
word format chosen during the previous conversion I/O se-
quence. The various formats and resolutions available are
shown in
Table 1
. In
Figure 8
, since 8-bit without sign MSB
first format was chosen during I/O sequence 4, the number
of SCLKs required during I/O sequence 5 is 8. In the follow-
ing I/O sequence the format changes to 12-bit without sign
MSB first; therefore the number of SCLKs required during
I/O sequence 6 changes accordingly to 12.
1.3 CS Low Continuously Considerations
When CS is continuously low, it is important to transmit the
exact number of SCLK pulses that the ADC expects. Not
doing so will desynchronize the serial communications to the
ADC. When the supply power is first applied to the ADC, it
will expect to see 13 SCLK pulses for each I/O transmission.
The number of SCLK pulses that the ADC expects to see is
the same as the digital output word length. The digital output
word length is controlled by the Data Out (DO) format. The
DO format maybe changed any time a conversion is started
or when the sign bit is turned on or off. The table below
details out the number of clock periods required for different
DO formats:
Number of
SCLKs
Expected
8
9
12
13
16
17
DO Format
8-Bit MSB or LSB First
SIGN OFF
SIGN ON
SIGN OFF
SIGN ON
SIGN OFF
SIGN ON
12-Bit MSB or LSB First
16-Bit MSB or LSB first
If erroneous SCLK pulses desynchronize the communica-
tions, the simplest way to recover is by cycling the power
supply to the device. Not being able to easily resynchronize
the device is a shortcoming of leaving CS low continuously.
The number of clock pulses required for an I/O exchange
may be different for the case when CS is left low continu-
ously vs the case when CS is cycled. Take the I/O sequence
detailed in
Figure 7
(Typical Power Supply Sequence) as an
example. The table below lists the number of SCLK pulses
required for each instruction:
Instruction
CS Low
Continuously
13 SCLKs
13 SCLKs
13 SCLKs
13 SCLKs
13 SCLKs
CS Strobed
Auto Cal
Read Status
Read Status
12-Bit + Sign Conv 1
12-Bit + Sign Conv 2
8 SCLKs
8 SCLKs
8 SCLKs
8 SCLKs
13 SCLKs
1.4 Analog Input Channel Selection
The data input on DI also selects the channel configuration
for a particular A/D conversion (see
Tables 2, 3, 4
and
Table
5
). In
Figure 8
the only times when the channel configuration
could be modified would be during I/O sequences 1, 4, 5 and
6. Input channels are reselected before the start of each new
conversion. Shown below is the data bit stream required on
DI, during I/O sequence number 4 in
Figure 8
, to set CH1 as
the positive input and CH0 as the negative input for the
different versions of ADCs:
Part
Number
ADC12H030
ADC12030
ADC12H032
ADC12032
ADC12H034
ADC12034
ADC12H038
ADC12038
Where X can be a logic high (H) or low (L).
DI Data
DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7
L
H
L
L
H
L
X
X
L
H
L
L
H
L
X
X
L
H
L
L
L
H
L
X
L
H
L
L
L
L
H
L
1.5 Power Up/Down
The ADC may be powered down at any time by taking the
PD pin HIGH or by the instruction input on DI (see
Tables 5,
6
, and the Power Up/Down timing diagrams). When the ADC
is powered down in this way, the circuitry necessary for an
A/D conversion is deactivated. The circuitry necessary for
digital I/O is kept active. Hardware power up/down is con-
trolled by the state of the PD pin. Software power-up/down is
controlled by the instruction issued to the ADC. If a software
power up instruction is issued to the ADC while a hardware
power down is in effect (PD pin high) the device will remain
in the power-down state. If a software power down instruc-
tion is issued to the ADC while a hardware power up is in
effect (PD pin low), the device will power down. When the
device is powered down by software, it may be powered up
by either issuing a software power up instruction or by taking
PD pin high and then low. If the power down command is
issued during an A/D conversion, that conversion is dis-
rupted. Therefore, the data output after power up cannot be
relied upon.
A
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