參數(shù)資料
型號: LM3881MMX
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 模擬信號調(diào)理
英文描述: Power Sequencer
中文描述: SPECIALTY ANALOG CIRCUIT, PDSO8
封裝: MSOP-8
文件頁數(shù): 10/14頁
文件大?。?/td> 218K
代理商: LM3881MMX
ENABLE CIRCUIT
The enable circuit is designed with an internal comparator,
referenced to a bandgap voltage (1.22V), to provide a preci-
sion threshold. This allows the timing to be set externally
using a capacitor as shown in the diagram below. Alterna-
tively, sequencing can be based on a certain event such as a
line voltage reaching 90% of its nominal value by employing
a resistor divider from VCC to Enable.
30048407
FIGURE 6. Precision Enable Circuit
Using the internal pull-up current source to charge the exter-
nal capacitor C
EN
, the time delay while the enable voltage
reaches the required threshold, assuming EN is charging
from 0V, can be calculated by the equation as follows.
30048404
FIGURE 7. Enable Delay Timing
A resistor divider can also be used to enable the LM3881
based on exceeding a certain VCC supply voltage threshold.
Care needs to be taken when sizing the resistor divider to
include the effects of the internal EN pull-up current source.
The supply voltage for which EN is asserted is given by
30048410
FIGURE 8. Enable Based On Input Supply Level
One of the features of the enable pin is that it provides glitch
free operation. The timer will start counting at a rising thresh-
old, but will always reset if the enable pin is de-asserted
before the first output flag is released. This is illustrated in the
timing diagram below, assuming INV is low.
30048411
FIGURE 9. Enable Glitch Timing, INV Low
If the EN pin remains high for the entire power up sequence,
then the part will operate as shown in the standard timing di-
agrams. However, if the EN signal is de-asserted before the
power-up sequence is completed, the part will enter a con-
trolled shutdown. This allows the system to initiate a con-
trolled power sequence, preventing any latch conditions to
occur. The following timing diagrams describe the flag se-
quence if the EN pin is de-asserted after FLAG1 releases, but
before the entire power-up sequence is completed. INV is as-
sumed low.
www.national.com
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