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參數(shù)資料
| 型號(hào)： | LM3880_07 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Power Sequencer |
| 中文描述： | 電力序 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大小： | 216K |
| 代理商： | LM3880_07 |
20192615
Cap Timing
Using the internal pull-up current source to charge the exter-
nal capacitor (C
) the enable pin delay can be calculated by
the equation below:
A resistor divider can also be used to enable the LM3880
based on a certain voltage threshold. Care needs to be taken
when sizing the resistor divider to include the effects of the
internal current source.
One of the features of the enable pin is that it provides glitch
free operation. The first timer will start counting at a rising
threshold, but will always reset if the enable pin is de-asserted
before the first output flag is released. This can be shown in
the timing diagram below:
20192617
EN Glitch
If the enable signal remains high for the entire power-up se-
quence, then the part will operate as shown in the standard
timing diagrams. However, if the enable signal is de-asserted
before the power-up sequence is completed the part will enter
a controlled shutdown. This allows the system to walk through
a controlled power cycling, preventing any latch conditions
from occuring. This state only occurs if the enable pin is de-
asserted after the completion of timer 1, but before the entire
power-up sequence is completed.
When this event occurs, the falling edge of enable pin resets
the current timer and will allow the remaining power-up cycle
to complete before beginning the power down sequence. The
power down sequence starts approximately 120ms after the
final power-up flag. This allows output voltages in the system
to stabilize before everything is shutdown. An example of this
operation can be seen below:
20192618
Incomplete Sequence
All the internal timers are generated by a master clock that
has an extremely low tempco. This allows for tight accuracy
across temperature and a consistent ratio between the indi-
vidual timers. There is a slight additional delay of approxi-
mately 400 μs to timers 1 and 4 which is a result of the
EPROM refresh. This refresh time is in addition to the pro-
grammed delay time and will be almost insignificant to all but
the shortest of timer delays.
www.national.com
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PDF描述 |
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| LM3880MF-1AA | Power Sequencer |
| LM3880MF-1AB | Power Sequencer |
| LM3880MF-1AC | Power Sequencer |
| LM3880MF-1AD | Power Sequencer |
| LM3880MFX-1AA | Power Sequencer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LM3880EVAL | 功能描述:電源管理IC開發(fā)工具 EVAL BOARD RoHS:否 制造商:Maxim Integrated 產(chǎn)品:Evaluation Kits 類型:Battery Management 工具用于評(píng)估:MAX17710GB 輸入電壓: 輸出電壓:1.8 V |
| LM3880MF-1 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Power Sequencer |
| LM3880MF-1AA | 功能描述:監(jiān)控電路 RoHS:否 制造商:STMicroelectronics 監(jiān)測(cè)電壓數(shù): 監(jiān)測(cè)電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| LM3880MF-1AA/NOPB | 功能描述:監(jiān)控電路 POWER SEQUENCER RoHS:否 制造商:STMicroelectronics 監(jiān)測(cè)電壓數(shù): 監(jiān)測(cè)電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| LM3880MF-1AB | 制造商:Texas Instruments 功能描述:Volt Supervisor Sequencer 6-Pin SOT-23 T/R 制造商:Texas Instruments 功能描述:IC, POWER SEQUENCER, SMD, SOT-23-6 |
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