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參數(shù)資料
| 型號(hào)： | LM3661TLX-1.40 |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 0.65 A SWITCHING REGULATOR, 675 kHz SWITCHING FREQ-MAX, PBGA10 |
| 封裝： | MICRO SMD-10 |
| 文件頁數(shù)： | 14/17頁 |
| 文件大?。?/td> | 845K |
| 代理商： | LM3661TLX-1.40 |
Electrical Characteristics (Note 2) (Continued)
Specifications with standard typeface are for T
J = 25C, and those in bold face type apply over the full Operating Temperature
Range (T
A =TJ = 30C to +85C). Unless otherwise specified, PVIN =VDD = EN = SYNC/MODE = VSEL = 3.6V, ISEL= 0V,
C
OUT = 22 F.
Symbol
Parameter
Remarks
Min
Typ
Max
Units
V
EN,H
EN Logic High Input (Note 4)
V
IN = 2.7V to 5.5V
1.2
V
EN,L
EN Logic Low Input
0.4
V
SYNC/MODE,
H
SYNC/MODE Logic High Input
1.2
V
SYNC/MODE,
L
SYNC/MODE Logic Low Input
0.4
V
SEL, H
V
SEL Logic High Input
1.2
V
SEL, L
V
SEL Logic Low Input
0.4
V
I
SEL,H
I
SEL Logic High Input
1.2
V
I
SEL, L
I
SEL Logic Low Input
0.4
R
EN
Enable pin input resistance
1
M
f
SYNC
SYNC/MODE Clock Frequency
Range (Note 6)
V
IN = 2.7V to 5.5V
500
750
kHz
f
OSC
Internal Oscillator Frequency
PWM mode (SYNC/MODE = V
IN)
V
IN = 2.7V to 5.5V
535
600
675
kHz
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of
the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the
Electrical Characteristics tables.
Note 2: Min and Max limits are guaranteed by design, test, or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm. Due
to the pulsed nature of the testing TA=TJ for the electrical characteristics table.
Note 3: Thermal shutdown will occur if the junction temperature exceeds 150C. This function is only active in PWM mode.
Note 4: The LM3202 is designed for mobile phone applications where turn-on after power-up is controlled by the system controller and where requirements for a
small package size overrule increased die size for internal Under Voltage Lock-Out (UVLO) circuitry. Thus, it should be kept in shutdown by holding the EN pin low
until the input voltage exceeds 2.7V.
Note 5: The hysteresis voltage is the minimum voltage swing on FB that causes the internal feedback and control circuitry to turn the internal PFET switch on and
then off, during test mode.
Note 6: SYNC/MODE driven with an external clock switching between VIN and GND. When an external clock is present at SYNC/MODE, the IC is forced to PWM
mode at the external clock frequency.
LM3661
www.national.com
6
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