
Glossary of Terms
(Continued)
This is also defined as the Low Cell
Charge Enable (LCCE) This way, deeply
discharged packs can be charged even if
the cell voltage is too low to enable the
logic to operate. See also, the M3 section
in the “Component Selection”.
Glossary of Specification
Parameters
V
MAX
The maximum steady state cell
voltage for disconnect mode.
The maximum cell voltage over-
shoot for conduction mode, re-
ferred to V
MAX
.
The minimum steady state cell
voltage for conduction mode.
The minimum cell voltage for
which
conduction
charging is guaranteed. Cell volt-
ages below this value will not be
charged, that is the MOSFET pair
will remain OFF. This feature en-
sures
that
very
charged cells will be chargeable.
The maximum pull-up voltage of
the
GATE
pin
mode.
The
pull-up
current
from the GATE pin in transition to
the conduction mode. This cur-
rent collapses to zero at GATE =
V
DD
.
The leakage current of the GATE
pin in disconnect mode.
The voltage across the MOSFET
pair that is used to detect if a
charger or a load is connected to
the battery pack. This voltage is
the difference between the V
and V
pins. The voltage be-
tween these pins is forced to
equal V
after a load
has been applied to an over-
charged pack in order to dis-
charge the pack without the
MOSFET cycling ON/OFF.
The maximum magnitude termi-
nal current allowed during charge
mode.
The maximum magnitude termi-
nal current allowed during dis-
charge mode.
The IC supply excluding the cur-
rent needed to supply the MOS-
FET turn-on current. The MOS-
FET turn-on current is calculated
by V
/R2
4 μA. The IC sup-
ply current flows between the
V
and V
pins. Additional cur-
rent can flow from the V
and
V
pins to the V pin when the
MOSFET pair is OFF and a
V
SAFE-OVER-CHARGE
V
MIN
V
MIN-CELL-CHARGE
mode
for
deeply
dis-
V
GATE-FETS-ON
in
conduction
I
GATE-FETS-ON
available
I
GATE-FETS-OFF
V
RECOVERY
I
MAX-CHG
I
MAX-DIS
I
SUPPLY
charger is applied to the pack.
This current is limited by the V
pin’s external resistor, R1.
The internal pulldown current for
the Enable pin; terminated at
V
SS
.
The time period between cell
voltage measurements.
The time period between cell
voltage measurements after 1
overcharge
measurement
before 4 normal cell voltage mea-
surements.
The time period for which the bat-
tery current must be greater than
the maximum current limit prior to
turning the MOSFET pair OFF.
Turn-on time (MOSFET pair V
>
V
) with 1 M
and 2 nF load at
the GATE pin.
The delay time after the Enable
pin is reconnected to V+ before
the MOSFET pair is allowed to
turn-on. This prevents switching
“chatter” of the MOSFET pair
during insertion to a charger or
load.
I
ENABLE PIN
t
SAMPLE
t
SAMPLE-4X
and
t
OVERCURRENT
t
FET-TURN-ON
t
ENABLE-RECOVERY
Component Selection
M1 & M2
The
power N-MOSFETs
must be able to isolate the cell from
invalid charge voltages, when the MOSFETs are OFF. The
breakdown voltage from drain to source determines the
maximum charger or reversed charger voltage tolerated. In-
valid chargers that exceed this breakdown voltage will allow
unlimited charge currents and therefore it is recommended
to provide secondary protection with passive thermal and/or
current fuses.
The maximum gate to source DC voltage is the cell voltage.
The V
may peak momentarily during the MOSFETs turn
ON from an OFF condition with a charger applied. This
causes the charger voltage to appear across the gate to
source voltage. So, choose MOSFETs than can withstand
this voltage.
The LM3641 has limited gate pin drive current and therefore,
the maximum V
rating of the MOSFETs must be higher
than the illegal charger voltage. The selection of the MOS-
FETs’ ON impedance is a pack power efficiency consider-
ation.
The MOSFETs maximum DC current operation should ex-
ceed the maximum rating of the LM3641’s overcurrent pro-
tection. Junction thermal conditions of the MOSFETs are of
prime importance in designing a reliable system. For ex-
ample, a dual MOSFET can have an I
rating of 5A. This
rating however is valid when either one of the MOSFETs is
ON. If both MOSFETs are ON, the rating for I
MAX
is less than
2.5A, because you have twice the R
power dissipation. Two single MOSFETs might give you a
better solution.
The peak currents encountered during short circuit are of
prime consideration in specifying the MOSFETs. The peak
current of parallel connected cells will be greater. Different
cell chemistries give different peak currents. The ON resis-
www.national.com
11