參數(shù)資料
型號(hào): LM3544MX-H/NOPB
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 電源管理
英文描述: 2-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO16
封裝: SOIC-16
文件頁數(shù): 2/13頁
文件大?。?/td> 785K
代理商: LM3544MX-H/NOPB
Application Information (Continued)
tantalum capacitor is recommended. The input supply
should be further bypassed with a 0.01 F - 0.1 F ceramic
capacitor, placed close to the device. The ceramic capacitor
reduces ringing on the supply that can occur when a short is
present at the output of a port.
EXTENDING THE FAULT FLAG DELAY
While the 7 ms (typical) internal delay in reporting flag con-
ditions is adequate for most applications, the delay can be
extended by connecting external RC filters to the FLAG pins,
as shown in Figure 5.
POWER DISSIPATION AND JUNCTION TEMPERATURE
A few simple calculations will allow a designer to calculate
the approximate operating temperature of the LM3544 for a
given application. The large currents possible through the
low resistance power MOSFET combined with the high ther-
mal resistance of the SOIC package, in relation to power
packages, make this estimate an important design step.
Begin the estimate by determining R
ON at the expected
operating temperature using the graphs in the Typical Per-
formance Characteristics section of this datasheet. Next,
calculate the power dissipation through the switch with
PD=R
ON *IDS
2
(1)
Note: Equation for power dissipation neglects portion that
comes from LM3544 quiescent current because this value
will almost always be insignificant.
Using this figure, determine the junction temperature with
T
J =PD*
θ
JA +TA.
(2)
Where:
θ
JA = SOIC Thermal Resistance: 130C/W and TA = Ambient
Temperature (C).
Compare the calculated temperature with the expected tem-
perature used to estimate R
ON. If they do not reasonably
match, re-estimate R
ON using a more appropriate operating
temperature and repeat the calculations. Reiterate as nec-
essary.
PCB LAYOUT CONSIDERATIONS
In order to meet the USB requirements for voltage drop,
droop and EMI, each component used in this circuit must be
evaluated for its contribution to the circuit performance.
These principles are illustrated in Figure 6. The following
PCB layout rules and guidelines are recommended
1.
Place the switch as close to the USB connector as
possible. Keep all V
bus traces as short as possible and
use at least 50-mil, 1 ounce copper for all V
bus traces.
Solder plating the traces will reduce the trace resistance.
2.
Avoid vias as much as possible. If vias are used, use
multiple vias in parallel and/or make them as large as
possible.
3.
Place the output capacitor and ferrite beads as close to
the USB connector as possible.
4.
If ferrite beads are used, use wires with minimum resis-
tance and large solder pads to minimize connection
resistance.
10120828
FIGURE 5. Typical Circuit for Lengthening the Internal
Flag Delay
10120827
FIGURE 6. Self-Powered Hub Connections and Per-Port Voltage Drop
LM3544
www.national.com
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