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switching noise can adversely affect the SNS or DIM pins. A
small capacitor for noise reduction will have little to no effect
on the LED ripple current or dimming but may help solve po-
tential EMI problems.
HG AND PFET SELECTION
When switching, the HG pin swings from V
(off state) to 4.7V
below V
(typical). As long as the DIM pin is high and the SNS
pin is below the upper threshold, HG will stay low, driving the
PFET on.
The PFET should be selected based on the maximum Drain-
Source voltage (V
), Drain current rating (Id), maximum
Gate-Source voltage (V
GS
), on-resistance (R
DS(on)
), and Gate
capacitance.
The voltage across the PFET in the off state is equal to the
sum of the input voltage and the diode forward voltage. The
V
DS
must therefore be selected to provide some margin be-
yond this voltage.
Since the peak current through the PFET is equal to the peak
current through the inductor, Id must be rated higher than the
maximum I
. The LM3401 is capable of 100% duty cy-
cle, therefore, the PFET drain current should be rated to
handle I
LED_PK
continuously. In this case there is no ripple, so
I
PK
= I
AVE
Although the typical HG voltage is V
- 4.7V, this voltage can
go much lower during the initial PFET turn-on time. How far
HG swings at turn-on depends on several factors including
the gate capacitance, on-time, and input voltage. As shown
in the Typical Performance Characteristics, the initial HG volt-
age swing increases with decreasing PFET gate capacitance.
Therefore, A PFET must be selected with a maximum V
rating larger than the initial HG voltage. Conversely, when
driving PFETs with larger gate capacitance, the initial HG
voltage will be lower. In some cases, a low V
threshold
PFET may be required to ensure complete turn-on. Use the
Typical Performance curve as a guideline to selecting a prop-
er PFET.
Note that HG will eventually settle around the typical voltage
of V
IN
- 4.7V regardless of the PFET gate capacitance.
HG has an absolute minimum voltage of 1.2V typically. When
the input voltage is below approximately 6V, this minimum
limit causes a reduction in drive voltage. At 5V input, for ex-
ample, HG will swing to 1.2V (or a gate drive voltage of -3.8V).
This may not be sufficient to drive some PFETs, and at this
reduced HG voltage, R
is likely to increase and trigger
current limit. Therefore, a low V
threshold PFET is also
recommended for lower input voltage applications.
The power loss in the PFET consists of switching losses and
conducting losses. Although switching losses are difficult to
precisely calculate, the equations below can be used to esti-
mate total power dissipation, which is the sum of PD
COND
and
PD
SW
.
PD
FET_COND
= R
DS(on)
x I
LED2
x D
Where P
= PFET turn-on time, P
= PFET turn-off time, and
D is the duty cycle. A value of 10 ns to 50 ns is typical for t
on
and t
. Longer PFET on and off times will degrade both effi-
ciency and accuracy.
Increasing R
DS(on)
will increase power losses and degrade ef-
ficiency. FET
RDS(on)
has a positive temperature coefficient. At
125°C, the R
DS(on)
may be as much as 150% higher than the
value at 25°C. The Gate capacitance of the PFET has a direct
impact on both PFET transition time and the power dissipation
in the LM3401. Most of the power dissipated in the LM3401
is used to drive the PFET switch. This power can be calcu-
lated as follows:
The average amount of gate driver current required during
switching (I
G
) is:
I
G
= Q
g
x f
SW
Where Q
g
is the PFET gate charge.
And the total power dissipated in the IC is:
PD = (Iq x V
IN
) + (I
G
x 4.7V)
Where Iq is typically 1.05 mA and 4.7V is the typical HG volt-
age.
Maximum power dissipation within the LM3401 is limited by
ambient temperature. Use the following equation to deter-
mine maximum allowable power dissipation, or maximum
allowable ambient temperature:
Where
θ
is the typical thermal resistance of 151°C/W. In
general, keeping the gate capacitance below 2000 pF is rec-
ommended to keep propagation delay, switching losses, and
power losses low. PFETs with very fast rise times may cause
excessive ringing at the HG node when combined with the
inductance of a long HG trace. To reduce this ringing, a small
resistor can be added between HG and the PFET gate. A
typical value of 10
is usually sufficient.
CURRENT LIMIT OPERATION
The LM3401 current limit monitors inductor current at each
switching cycle. Current is sensed across the R
of the
PFET at the CS pin. When the PFET current exceeds the
current limit threshold, HG is turned off and the current limit
latch is set. In current limit mode, the PFET is held off until the
inductor current falls to near zero.
30021431
FIGURE 6. Typical Current Limit Operation
The current limit threshold is adjusted with a setting resistor,
shown as R3 in the typical application schematic, connected
from I
LIM
to the V
IN
node of the PFET.
An internal 5.5 μA (typical) current sink at the ILIM pin creates
a voltage across the setting resistor. This voltage is compared
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