參數(shù)資料
型號(hào)： LM3401
廠商： National Semiconductor Corporation
英文描述： Hysteretic PFET Controller for High Power LED Drive
中文描述： 遲滯PFET的控制器的高功率LED驅(qū)動(dòng)
文件頁(yè)數(shù)： 10/18頁(yè)
文件大小： 324K
代理商： LM3401
to the sensed voltage at the CS pin. Current limit is activated
and latched when the voltage at the CS pin drops below the
voltage at the ILIM pin.
The current limit setting resistor, R3, can be calculated from
the equation below. The minimum current limit occurs at max-
imum R
DS(on)
and minimum I
ILIM
value.
Where 4 μA is the minimum I
value and I
is the peak
inductor current limit threshold. I
should be set some-
what higher than the maximum LED current, I
LED_PK
, to avoid
false current limit triggering. The temperature variation of the
PFET R
will result in an equivalent variation in current
limit. To ensure that current limit is not falsely triggered, use
the highest R
DS(on)
value over the temperature range to set
the R3 value.
When current limit is activated, the HG driver remains off until
the CS voltage rises to -130 mV (typical). This ensures that
inductor current is close to 0A when the current limit latch is
released. The actual minimum inductor current will depend on
the catch diode forward voltage characteristic, which deter-
mines the CS pin negative voltage.
Although the LM3401 monitors voltage at the CS pin to reset
the current limit, there is also a minimum off time of typically
3 μs. When current limit is triggered, HG will be turned off for
at least this amount of time, regardless of the inductor current.
The current limit comparator imposes typically 150 ns of
blanking time at the beginning of each switching cycle. This
ensures that the PFET is fully on and any switch node ringing
has dissipated when the current is sensed. However a slower
PFET may not fully turn on within the blanking time. In this
case, the current limit threshold must be increased or a faster
PFET must be used.
Because the current limit comparator has a limited differential
voltage capability, a maximum of 1M
is recommended for
R3.
PWM DIMMING
The DIM pin is a CMOS compatible input for a PWM (Pulse
Width Modulation) dimming signal. PWM dimming adjusts
LED brightness by varying the duty cycle, which varies the
average LED current. This type of dimming is recommended,
because LED peak current remains constant regardless of
brightness, which results in more predictable LED color and
performance as compared to analog dimming.
Figure 7
shows a typical PWM dimming waveform.
When DIM is high (above 2V typically) the LM3401 operates
normally and the LED string will be driven at the set current.
When pulled low, DIM will disable HG and switching will stop.
The PFET will remain off as long as DIM is low. When the
LM3401 is powered up or enabled with the DIM pin, the LED
current will very rapidly increase to its set point.
There is minimal delay time between a DIM logic change and
HG switching. Also, because the LM3401 requires no output
capacitor, minimal time is required to ramp-up the LED cur-
rent. This allows for low duty cycle, high frequency PWM
dimming signals to be used.
A dimming frequency greater than 100 Hz is recommended
to avoid visible flicker. The LM3401 is capable of PWM dim-
ming frequencies up to 10 kHz with a duty cycle between 1
and 100%. Any DIM signal pulse width longer than 100 ns can
be used. In most cases, the maximum dimming frequency is
limited by the inductor size and input voltage to anode voltage
ratio. Less inductance and higher V
/V
ratios will allow
the inductor and LED current to increase faster, thus allowing
for a faster PWM frequency, or lower dimming duty cycle.
30021433
FIGURE 7. Typical PWM DIM Signal and LED Current
L = 22 μH
DIM is a high impedance pin, which is somewhat sensitive to
noise. If there is excessive switching noise at the DIM pin, a
small bypass filter capacitor can be used. See the Ripple Re-
duction Capacitor section. V
can also be used for PWM
dimming when a logic signal is not available. In this mode of
operation DIM should be connected to V
through a 10 k
resistor. There is typically 10 us of startup delay time when
using V
for dimming. Depending on the application, this de-
lay limits the maximum dimming frequency to typically several
hundred Hz.
Higher dimming frequency and lower dimming duty cycle can
be achieved by using a FET switch in parallel with the LED
string. This is shown in
Figure 8
below.
30021434
FIGURE 8. Parallel FET Dimming
When the FET switches on, inductor current flows through the
FET and the regulated average inductor current is un-
changed. Using this method, inductor current rise time does
not limit the dimming frequency. A ripple reduction capacitor
should not be used with the parallel FET dimming method
since it significantly slows the LED current rise time. However,
a small noise filter capacitor can be used.
INPUT CAPACITOR SELECTION
An input bypass capacitor is required between V
and
ground. The input capacitor prevents large voltage transients
www.national.com
10
L
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