參數(shù)資料
型號(hào): LM3370TL-2613/NOPB
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 穩(wěn)壓器
英文描述: 1.4 A DUAL SWITCHING CONTROLLER, 2400 kHz SWITCHING FREQ-MAX, PBGA20
封裝: 3 X 2 MM, 0.60 MM HEIGHT, 0.50 MM PITCH, , MO-211DG, MICRO, SMD-20
文件頁(yè)數(shù): 9/26頁(yè)
文件大?。?/td> 5436K
代理商: LM3370TL-2613/NOPB
TRANSFERRING DATA
Every byte put on the SDA line must be eight bits long, with
the most significant bit (MSB) being transferred first. The
number of bytes that can be transmitted per transfer is unre-
stricted. Each byte of data has to be followed by an acknowl-
edge bit. The acknowledge related clock pulse is generated
by the master. The transmitter releases the SDA line (HIGH)
during the acknowledge clock pulse. The receiver must pull
down the SDA line during the 9th clock pulse, signifying an
acknowledge. A receiver which has been addressed must
generate an acknowledge after each byte has been received.
After the START condition, I2C master sends a chip address.
This address is seven bits long followed by an eighth bit which
is a data direction bit (R/W). For the eighth bit, a “0” indicates
a WRITE and a “1” indicates a READ. The second byte se-
lects the register to which the data will be written. The third
byte contains data to write to the selected register.
I2C-Compatible Write Cycle
20167309
W = write (SDA = “0”)
r = read (SDA = “1”)
ack = acknowledge (SDA pulled down by either master or slave)
rs = repeated startxx=36h
However, if a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in the read
cycle waveform.
I2C-Compatible Read Cycle
20167310
17
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LM3370
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