參數(shù)資料
型號: LM3311SQX
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 穩(wěn)壓器
英文描述: Step-Up PWM DC/DC Converter with Integrated LDO, Op-Amp, and Gate Pulse Modulation Switch
中文描述: 2.6 A SWITCHING REGULATOR, 1280 kHz SWITCHING FREQ-MAX, QCC24
封裝: LLP-24
文件頁數(shù): 20/29頁
文件大?。?/td> 2052K
代理商: LM3311SQX
Operation
(Continued)
pump is a discrete solution driven from the SW pin and the
output of the boost switching regulator. When VFLK is high,
the PMOS switch P2 is turned on and the PMOS switch P3
is turned off. With P2 on, the VGHM pin is pulled to the same
voltage applied to the VGH pin. This provides a high gate
drive voltage, VGHM
, and can source current to the gate
drive circuitry. When VFLK is high, NMOS switch N3 is on
which discharges the capacitor CE.
When VFLK is low, the NMOS switch N3 is turned off which
allows current to charge the C
capacitor. This creates a
delay, t
DELAY
, given by the following equations:
t
DELAY
)
1.265V(C
E
+ 15pF)/I
CE
When the voltage on CE reaches about 1.265V and the
VFLK signal is low, the PMOS switch P2 will turn off and the
PMOS switch P3 will turn on connecting resistor R3 to the
VGHM pin through P3. This will discharge the voltage at
VGHM at some rate determined by R3 creating a slope, M
,
as shown in
Figure 2
. The VGHM pin is no longer a current
source, it is now sinking current from the gate drive circuitry.
As VGHM is discharged through R3, the comparator con-
nected to the pin V
DD
monitors the VGHM voltage. PMOS
switch P3 will turn off when the following is true:
VGHM
MIN
)
10V
X
R2/(R1 + R2)
where V
X
is some voltage connected to the resistor divider
on pin V
DD
. V
X
is typically connected to the output of the
boost switching regulator. When PMOS switch P3 turns off,
VGHM will be high impedance until the VFLK pin is high
again.
Figure 3
and
Figure 4
the GPM block. Waveform (1) is the VGHM pin, (2) is the
VFLK and (3) is the VDPM. The output of the boost switching
regulator is operating at 8.5V and there is a 3x discrete
charge pump (~23.5V) supplying the VGH pin. In
Figure 3
and
Figure 4
, the VGHM pin is driving a purely capacitive
load, 4.7nF. The value of resistor R1 is 15kohm, R2 is 1.1k
and R3 is 750
. In both transient plots, there is no C
E
delay
capacitor.
In the GPM block diagram, a signal called “Reset” is shown.
This signal is generated from the V
under-voltage lockout,
thermal shutdown, or the SHDN pin. If the V
IN
supply voltage
drops below 2.3V, typically, then the GPM block will be
disabled and the VGHM pin will discharge through NMOS
switch N2 and the 1k
resistor. This applies also if the
junction temperature of the device exceeds 145C or if the
SHDN signal is low. As shown in the block diagram, both
VDPM and VFLK have internal 350k
pull down resistors.
This puts both VDPM and VFLK in normally “off” states.
Typical VDPM and VFLK pin currents can be found in the
Typical Performance Characteristics
section.
20126384
FIGURE 2.
20126385
FIGURE 3.
20126386
FIGURE 4.
L
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