參數(shù)資料
型號(hào): LM3311SQ-HIOP/NOPB
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 穩(wěn)壓器
英文描述: 2.6 A SWITCHING REGULATOR, 1280 kHz SWITCHING FREQ-MAX, QCC24
封裝: LEAD FREE, LLP-24
文件頁數(shù): 16/32頁
文件大小: 2504K
代理商: LM3311SQ-HIOP/NOPB
capacitor size can often be reduced. The size can also be
reduced if the input of the regulator is very close to the source
output. The size will generally need to be larger for applica-
tions where the regulator is supplying nearly the maximum
rated output or if large load steps are expected. A minimum
value of 10F should be used for the less stressful condtions
while a 22F to 47F capacitor may be required for higher
power and dynamic loads. Larger values and/or lower ESR
may be needed if the application requires very low ripple on
the input source voltage.
The choice of output capacitors is also somewhat arbitrary
and depends on the design requirements for output voltage
ripple. It is recommended that low ESR (Equivalent Series
Resistance, denoted R
ESR) capacitors be used such as ce-
ramic, polymer electrolytic, or low ESR tantalum. Higher ESR
capacitors may be used but will require more compensation
which will be explained later on in the section. The ESR is also
important because it determines the peak to peak output volt-
age ripple according to the approximate equation:
ΔV
OUT 2ΔiLRESR (in Volts)
A minimum value of 10F is recommended and may be in-
creased to a larger value. After choosing the output capacitor
you can determine a pole-zero pair introduced into the control
loop by the following equations:
Where R
L is the minimum load resistance corresponding to
the maximum load current. The zero created by the ESR of
the output capacitor is generally very high frequency if the
ESR is small. If low ESR capacitors are used it can be ne-
glected. If higher ESR capacitors are used see the High
Output Capacitor ESR Compensation section. Some suitable
capacitor vendors include Vishay, Taiyo-Yuden, and TDK.
RIGHT HALF PLANE ZERO
A current mode control boost regulator has an inherent right
half plane zero (RHP zero). This zero has the effect of a zero
in the gain plot, causing an imposed +20dB/decade on the
rolloff, but has the effect of a pole in the phase, subtracting
another 90° in the phase plot. This can cause undesirable
effects if the control loop is influenced by this zero. To ensure
the RHP zero does not cause instability issues, the control
loop should be designed to have a bandwidth of less than
the frequency of the RHP zero. This zero occurs at a fre-
quency of:
where I
LOAD is the maximum load current.
SELECTING THE COMPENSATION COMPONENTS
The first step in selecting the compensation components R
C
and C
C is to set a dominant low frequency pole in the control
loop. Simply choose values for R
C and CC within the ranges
given in the Introduction to Compensation section to set this
pole in the area of 10Hz to 500Hz. The frequency of the pole
created is determined by the equation:
where R
O is the output impedance of the error amplifier, ap-
proximately 900k
. Since R
C is generally much less than
R
O, it does not have much effect on the above equation and
can be neglected until a value is chosen to set the zero f
ZC.
f
ZC is created to cancel out the pole created by the output
capacitor, f
P1. The output capacitor pole will shift with different
load currents as shown by the equation, so setting the zero is
not exact. Determine the range of f
P1 over the expected loads
and then set the zero f
ZC to a point approximately in the mid-
dle. The frequency of this zero is determined by:
Now R
C can be chosen with the selected value for CC. Check
to make sure that the pole f
PC is still in the 10Hz to 500Hz
range, change each value slightly if needed to ensure both
component values are in the recommended range.
HIGH OUTPUT CAPACITOR ESR COMPENSATION
When using an output capacitor with a high ESR value, or just
to improve the overall phase margin of the control loop, an-
other pole may be introduced to cancel the zero created by
the ESR. This is accomplished by adding another capacitor,
C
C2, directly from the compensation pin VC to ground, in par-
allel with the series combination of R
C and CC. The pole
should be placed at the same frequency as f
Z1, the ESR zero.
The equation for this pole follows:
To ensure this equation is valid, and that C
C2 can be used
without negatively impacting the effects of R
C and CC, fPC2
must be greater than 10f
ZC.
CHECKING THE DESIGN
With all the poles and zeros calculated the crossover fre-
quency can be checked as described in the section DC Gain
and Open-loop Gain. The compensation values can be
changed a little more to optimize performance if desired. This
is best done in the lab on a bench, checking the load step
response with different values until the ringing and overshoot
on the output voltage at the edge of the load steps is minimal.
This should produce a stable, high performance circuit. For
improved transient response, higher values of R
C should be
chosen. This will improve the overall bandwidth which makes
the regulator respond more quickly to transients. If more detail
is required, or the most optimum performance is desired, refer
to a more in depth discussion of compensating current mode
DC/DC switching regulators.
POWER DISSIPATION
The output power of the LM3311 is limited by its maximum
power dissipation. The maximum power dissipation is deter-
mined by the formula
P
D = (Tjmax - TA)/θJA
where T
jmax is the maximum specified junction temperature
(125°C), T
A is the ambient temperature, and θJA is the thermal
resistance of the package.
23
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LM3311
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