參數(shù)資料
型號(hào): LM3218SE
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 穩(wěn)壓器
英文描述: SWITCHING REGULATOR, DSO8
封裝: LTCC-8
文件頁(yè)數(shù): 6/16頁(yè)
文件大?。?/td> 4709K
代理商: LM3218SE
TABLE 1. Suggested Capacitors And Their Suppliers
Model
Vendor
C1608X5R0J106K, 10 F, 6.3V
TDK
C1608X5R0J475M, 4.7 F, 6.3V
TDK
0805ZD475KA 4.7 F, 10V
AVX
The input filter capacitor supplies AC current drawn by the
PFET switch of the LM3218 in the first part of each cycle and
reduces the voltage ripple imposed on the input power
source. The output filter capacitor absorbs the AC inductor
current, helps maintain a steady output voltage during tran-
sient load changes and reduces output voltage ripple. These
capacitors must be selected with sufficient capacitance and
sufficiently low ESR (Equivalent Series Resistance) to per-
form these functions. The ESR of the filter capacitors is
generally a major factor in voltage ripple.
EN PIN CONTROL
Drive the EN pin using the system controller to turn the
LM3218 ON and OFF. Use a comparator, Schmidt trigger or
logic gate to drive the EN pin. Set EN high (>1.2V) for normal
operation and low (<0.5V) for a 0.01
μA (typ.) shutdown mode
and requirements for small package size outweigh the addi-
tional size required for inclusion of UVLO (Under Voltage
Lock-Out) circuitry.
LTCC PACKAGE ASSEMBLY AND USE
The LTCC Integrated Inductor withLM3218 micro SMD pack-
age is optimized for the smallest possible size in applications
with red or infrared opaque cases. Because the micro SMD
package lacks the plastic encapsulation characteristic of larg-
er devices, it is vulnerable to light. Backside metalization and/
or epoxy coating, along with front-side shading by the printed
circuit board, reduce this sensitivity. However, the package
has exposed die edges. In particular, micro SMD devices are
sensitive to light, in the red and infrared range, shining on the
package’s exposed die edges.
BOARD LAYOUT CONSIDERATIONS
30050408
FIGURE 4. Current Loop
The LM3218 converts higher input voltage to lower output
voltage with high efficiency. This is achieved with an inductor-
based switching topology. During the first half of the switching
cycle, the internal PMOS switch turns on, the input voltage is
applied to the inductor, and the current flows from PV
IN line
into the output capacitor and the load through the inductor.
During the second half cycle, the PMOS turns off and the in-
ternal NMOS turns on. The inductor current continues to flow
via the inductor from the device PGND line into the output
capacitor and the load.
Referring to Figure 4, a pulse current flows in the left-hand
side loop, and a ripple current flows in the right-hand side
loop. Board layout and circuit pattern design of these two
loops are the key factors for reducing noise radiation and sta-
ble operation. In other lines, such as from battery to C1 and
C2 to the load, the current is mostly DC current. Therefore, it
is not necessary to take so much care. Only pattern width
(current capability) and DCR drop considerations are needed.
30050459
FIGURE 5. Evaluation Board Layout
www.national.com
14
LM3218
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