參數(shù)資料
型號: LM3204
廠商: National Semiconductor Corporation
元件分類: DC/DC變換器
英文描述: Miniature, Adjustable, Step-Down DC-DC Converter with Bypass Mode for RF Power Amplifiers
中文描述: 微型,可調(diào),降壓的DC - DC轉(zhuǎn)換器旁路模式射頻功率放大器
文件頁數(shù): 4/16頁
文件大?。?/td> 874K
代理商: LM3204
Electrical Characteristics
(Notes 2, 7) Limits in standard typeface are for T
A
= T
J
= 25C. Limits in
boldface
type apply over the full operating ambient temperature range (30C
T
A
= T
J
+85C). Unless otherwise noted,
specifications apply to the LM3204 with: PV
IN
= V
DD
= EN = 3.6V, BYP = 0V. (Continued)
Symbol
V
IL
Parameter
Conditions
Min
Typ
Max
Units
Logic Low Input
Threshold for EN, BYP
Pin Pull Down Current
for EN, BYP
V
CON
to V
OUT
Gain
V
CON
Input Leakage
Current
0.4
V
I
PIN
EN, BYP = 3.6V
5
10
μA
Gain
I
CON
3
V/V
V
CON
= 1.2V
10
nA
System Characteristics
in the typical application circuit are used.
These parameters are not guaranteed by production testing.
The following spec table entries are guaranteed by design if the component values
Symbol
T
RESPONSE
Parameter
Conditions
Min
Typ
Max
Units
Time for V
OUT
to Rise from
0.8V to 3.4V in PWM Mode
V
IN
= 4.2V, C
OUT
= 4.7μF,
R
LOAD
= 15
L = 2.2 μH (I
SAT
>
0.94A)
V
IN
= 4.2V, C
OUT
= 4.7μF,
R
LOAD
= 15
L = 2.2μH (I
SAT
= 0.94A)
EN = Low to High
V
CON
= 1V,
Test frequency = 100kHz
V
IN
= 3.6V, V
CON
= 0.267V,
C
OUT
= 4.7μF, R
LOAD
= 15
BYP = Low to High
(Note 10)
25
μs
T
STARTUP
Time for V
OUT
to rise to 3.4V
in PWM Mode
(Note 14)
50
μs
C
CON
V
CON
Input Capacitance
15
pF
T
ON_BYP
Bypass FET Turn On Time
In Bypass Mode
30
μs
T
BYP
Auto Bypass Detect Delay
Time
10
15
20
μs
Note 1:
Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of
the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the
Electrical Characteristics tables.
Note 2:
All voltages are with respect to the potential at the GND pins.
Note 3:
Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at T
J
= 150C (typ.) and disengages at T
J
=
130C (typ.).
Note 4:
The Human body model is a 100pF capacitor discharged through a 1.5k
resistor into each pin. (MIL-STD-883 3015.7) The machine model is a 200pF
capacitor discharged directly into each pin. National Semiconductor recommends that all integrated circuits be handled with appropriate precautions. Failure to
observe proper ESD handling techniques can result in damage.
Note 5:
In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be
de-rated. Maximum ambient temperature (T
A-MAX
) is dependent on the maximum operating junction temperature (T
J-MAX-OP
= 125C), the maximum power
dissipation of the device in the application (P
D-MAX
), and the junction-to ambient thermal resistance of the part/package in the application (
θ
JA
), as given by the
following equation: T
A-MAX
= T
J-MAX-OP
– (
θ
JA
x P
D-MAX
).
Note 6:
Junction-to-ambient thermal resistance (
θ
JA
) is taken from thermal measurements, performed under the conditions and guidelines set forth in the JEDEC
standard JESD51-7. A 1" x 1", 4 layer, 1.5oz. Cu board was used for the measurements.
Note 7:
Min and Max limits are guaranteed by design, test, or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm.
Note 8:
The LM3204 is designed for mobile phone applications where turn-on after power-up is controlled by the system controller and where requirements for a
small package size overrule increased die size for internal Under Voltage Lock-Out (UVLO) circuitry. Thus, it should be kept in shutdown by holding the EN pin low
until the input voltage exceeds 2.7V.
Note 9:
Over-Voltage protection (OVP) threshold is the voltage above the nominal V
OUT
where the OVP comparator turns off the PFET switch while in PWM mode.
Note 10:
V
IN
is compared to the programmed output voltage (V
OUT
). When V
IN
–V
OUT
falls below V
BYPASS
for longer than T
the Bypass FET turns on and the
switching FETs turn off. This is called the Bypass mode. The device comes out of Bypass mode when V
–V
exceeds V
BYBYP
for longer than T
, and PWM
mode returns. The hysteresis for the bypass detection threshold V
BYPASS+
– V
BYPASS
will always be positive and will be approximately 200mV (typ.).
Note 11:
Shutdown current includes leakage current of PFET and Bypass FET.
Note 12:
Electrical Characteristic table reflects open loop data (FB=0V and current drawn from SW pin ramped up until cycle by cycle current limit is activated).
Refer to datasheet curves for closed loop data and its variation with regards to supply voltage and temperature. Closed loop current limit is the peak inductor current
measured in the application circuit by increasing output current until output voltage drops by 10%.
Note 13:
Bypass FET current limit is defined as the load current at which the FB voltage is 1V lower than V
IN
.
Note 14:
The startup time is the time to reach 90% of 3.4V nominal output voltage from the EN being low to high.
L
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