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參數(shù)資料
| 型號： | LM2984MDC |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, UUC |
| 封裝： | DIE |
| 文件頁數(shù)： | 4/16頁 |
| 文件大?。?/td> | 317K |
| 代理商： | LM2984MDC |
Application Hints (Continued)
the standby mode It is also fault protected against overvolt-
age and thermal overload If the input voltage rises above
approximately 30V (eg load dump) this output will auto-
matically shut down This protects the internal circuitry and
enables the IC to survive higher voltage transients than
would otherwise be expected Thermal shutdown is neces-
sary since this output is one of the dominant sources of
power dissipation in the IC
MAIN OUTPUT
The main output is designed to power relatively large loads
ie approximately 500 mA It is therefore also protected
against overvoltage and thermal overload
This output will track the other two within a few millivolts in
normal operation It can therefore be used as a reference
voltage for any signal derived from circuitry powered off the
standby or buffer outputs This is important in a ratiometric
sensor system or any system requiring accurate matching of
power supply voltages
ONOFF SWITCH
The ONOFF switch controls the main output and the buffer
output The threshold voltage is compatible with most logic
families and has about 20 mV of hysteresis to insure ‘clean’
switching from the standby mode to the active mode and
vice versa This pin can be tied to the input voltage through
a10kX resistor if the regulator is to be powered continu-
ously
POWER DOWN OVERRIDE
Another possible approach is to use a diode in series with
the ONOFF signal and another in series with the main out-
put in order to maintain power for some period of time after
the ONOFF signal has been removed (see
Figure 1 ) When
the ONOFF switch is initially pulled high through diode D1
the main output will turn on and supply power through diode
D2 to the ONOFF switch effectively latching the main out-
put An open collector transistor Q1 is connected to the
ONOFF pin along with the two diodes and forces the regu-
lators off after a period of time determined by the mP In this
way the mP can override a power down command and store
data do housekeeping etc before reverting back to the
standby mode
TLH8821 – 10
FIGURE 1 Power Down Override
RESET OUTPUT
This output is an open collector NPN transistor which is
forced low whenever an error condition is present at the
main output or when a mP error is sensed (see mP Monitor
section) If the main output voltage drops below 4V or rises
above 55V the RESET output is forced low and held low
for a period of time set by two external components Rt and
Ct There is a slight amount of hysteresis in these two
threshold voltages so that the RESET output has a fast rise
and fall time compatible with the requirements of most mP
RESET inputs
DELAYED RESET
Resistor Rt and capacitor Ct set the period of time that the
RESET output is held low after a main output error condition
has been sensed The delay is given by the formula
Tdly e 12 RtCt (seconds)
The delayed RESET will be initiated any time the main out-
put is outside the 4V to 55V window ie during power-up
short circuit overvoltage low line thermal shutdown or
power-down The mP is therefore RESET whenever the out-
put voltage is out of regulation (It is important to note that a
RESET is only initiated when the main output is in error The
buffer and standby outputs are not directly monitored for
error conditions)
mP MONITOR RESET
There are two distinct and independent error monitoring
systems in the LM2984C The one described above moni-
tors the main regulator output and initiates a delayed RE-
SET whenever this output is in error The other error moni-
toring system is the mP watchdog These two systems are
OR’d together internally and both force the RESET output
low when either type of error occurs
This watchdog circuitry continuously monitors a pin on the
m
P that generates a positive going pulse during normal op-
eration The period of this pulse is typically on the order of
milliseconds and the pulse width is typically on the order of
10’s of microseconds If this pulse ever disappears the
watchdog circuitry will time out and a RESET low will be
sent to the mP The time out period is determined by two
external components Rt and Cmon according to the formu-
la
Twindow e 082 RtCmon (seconds)
The width of the RESET pulse is set by Cmon and an inter-
nal resistor according to the following
RESETpw e 2000 Cmon (seconds)
A square wave signal can also be monitored for errors by
filtering the Cmon input such that only the positive edges of
the signal are detected
Figure 2 is a schematic diagram of a
typical circuit used to differentiate the input signal Resistor
Rtc and capacitor Ctc pass only the rising edge of the
square wave and create a short positive pulse suitable for
the mP monitor input If the incoming signal continues in a
high state or in a low state for too long a period of time a
RESET low will be generated
TLH8821 – 11
FIGURE 2 Monitoring Square Wave mP Signals
The threshold voltage and input characteristics of this pin
are compatible with nearly all logic families
There is a limit on the width of a pulse that can be reliably
detected by the watchdog circuit This is due to the output
resistance of the transistor which discharges Cmon when a
high state is detected at the input The minimum detectable
pulse width can be determined by the following formula
PWmin e 20 Cmon (seconds)
12
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